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Changeset 0a78e4f in mainline


Ignore:
Timestamp:
2017-08-22T16:08:00Z (3 years ago)
Author:
Martin Decky <martin@…>
Branches:
master
Children:
b93ea46
Parents:
d639eaa
Message:

riscv64: cycle performance counter

Files:
2 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/riscv64/src/asm.S

    rd639eaa r0a78e4f  
    3030#include <arch/arch.h>
    3131#include <arch/mm.h>
     32
     33#define MCOUNTEREN_CY_MASK  0x00000001
     34#define MCOUNTEREN_TM_MASK  0x00000002
     35#define MCOUNTEREN_IR_MASK  0x00000004
    3236
    3337#define MSTATUS_MPP_MASK        0x00001800
     
    9195
    9296FUNCTION_BEGIN(jump_to_kernel)
     97        /* Enable performance counters access in supervisor mode */
     98        csrsi mcounteren, MCOUNTEREN_CY_MASK | MCOUNTEREN_TM_MASK | MCOUNTEREN_IR_MASK
     99       
    93100        /* Setup SV48 paging for supervisor mode */
    94101        la t0, ptl_0
     
    108115        li t1, ~MSTATUS_MPP_MASK
    109116        and t0, t0, t1
    110        
    111117       
    112118        /*
  • kernel/arch/riscv64/include/arch/cycle.h

    rd639eaa r0a78e4f  
    4040NO_TRACE static inline uint64_t get_cycle(void)
    4141{
    42         return 0;
     42        uint64_t cycle;
     43       
     44        asm volatile (
     45                "rdcycle %[cycle]\n"
     46                : [cycle] "=r" (cycle)
     47        );
     48       
     49        return cycle;
    4350}
    4451
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