Changeset 0a78e4f in mainline for boot/arch/riscv64/src/asm.S

Timestamp:

2017-08-22T16:08:00Z (7 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b93ea46a

Parents:

d639eaa

Message:

riscv64: cycle performance counter

File:

• boot/arch/riscv64/src/asm.S (modified) (3 diffs)

boot/arch/riscv64/src/asm.S

@@ -30 +30 @@
 #include <arch/arch.h>
 #include <arch/mm.h>
+
+#define MCOUNTEREN_CY_MASK  0x00000001
+#define MCOUNTEREN_TM_MASK  0x00000002
+#define MCOUNTEREN_IR_MASK  0x00000004
 
 #define MSTATUS_MPP_MASK        0x00001800
@@ -91 +95 @@
 
 FUNCTION_BEGIN(jump_to_kernel)
+        /* Enable performance counters access in supervisor mode */
+        csrsi mcounteren, MCOUNTEREN_CY_MASK | MCOUNTEREN_TM_MASK | MCOUNTEREN_IR_MASK
+        
         /* Setup SV48 paging for supervisor mode */
         la t0, ptl_0
@@ -108 +115 @@
         li t1, ~MSTATUS_MPP_MASK
         and t0, t0, t1
-        
         
         /*