Changeset 0867321 in mainline for kernel/arch/ppc32/src/mm/tlb.c
- Timestamp:
- 2009-02-02T18:06:15Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- cdda403
- Parents:
- 7b187ef
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ppc32/src/mm/tlb.c
r7b187ef r0867321 228 228 229 229 230 /** Process Instruction/Data Storage Interrupt231 * 232 * @param n Interruptvector number.233 * @param istate 230 /** Process Instruction/Data Storage Exception 231 * 232 * @param n Exception vector number. 233 * @param istate Interrupted register context. 234 234 * 235 235 */ … … 288 288 289 289 290 /** Process Instruction/Data Storage Interruptin Real Mode291 * 292 * @param n Interruptvector number.293 * @param istate 290 /** Process Instruction/Data Storage Exception in Real Mode 291 * 292 * @param n Exception vector number. 293 * @param istate Interrupted register context. 294 294 * 295 295 */ … … 406 406 407 407 return true; 408 } 409 410 411 /** Process ITLB/DTLB Miss Exception in Real Mode 412 * 413 * 414 */ 415 void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) 416 { 417 uint32_t badvaddr = tlbmiss & 0xfffffffc; 418 419 uint32_t physmem; 420 asm volatile ( 421 "mfsprg3 %0\n" 422 : "=r" (physmem) 423 ); 424 425 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) 426 return; // FIXME 427 428 ptelo.rpn = KA2PA(badvaddr) >> 12; 429 ptelo.wimg = 0; 430 ptelo.pp = 2; // FIXME 431 432 uint32_t index = 0; 433 asm volatile ( 434 "mtspr 981, %0\n" 435 "mtspr 982, %1\n" 436 "tlbld %2\n" 437 "tlbli %2\n" 438 : "=r" (index) 439 : "r" (ptehi), 440 "r" (ptelo) 441 ); 408 442 } 409 443
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