Generic address translation miss handler for the kernel address space

[Martin Decky]

We need a generic address translation miss handler for the kernel address space and special "locked" user address space areas (e.g. for IRQ handlers and DMA memory) which would work with atomic operations only and which would not require any locking.

[Martin Decky]

Initial implementation has been provided for ppc32 in mainline,981, pending review. I suggest keeping this ticket open for a while since I believe there is still space to generalize the solution for all platforms.

[Jakub Jermář]

All architectures now have some mechanism to provide the kernel identity and kernel non-identity. For identity, the mechanism varies from architecture to architecture and can range from determined by hardware, through preset in hardware-walked page tables to provided by the TLB miss handler. All kernels can handle kernel non-identity mappings, and the logic was modified not to hold the address space lock.