Opened 15 years ago
Last modified 6 years ago
#16 new enhancement
mips32 loaders need to maintain cache coherence
| Reported by: | Jakub Jermář | Owned by: | |
|---|---|---|---|
| Priority: | major | Milestone: | |
| Component: | helenos/boot/mips32 | Version: | mainline |
| Keywords: | Cc: | ||
| Blocker for: | Depends on: | ||
| See also: |
Description (last modified by )
The mips32 loader needs to establish cache coherence after it copies the kernel and other components around memory (corner case of self modifying code).
arm32 already does the right thing.
sparc64 already does the right thing.
ppc32 seems to flush something, but the issue still needs to be investigated/confirmed.
ia64, as of now, does not relocate neither the kernel nor the components so the caches are coherent.
Change History (4)
comment:1 by , 14 years ago
| Component: | → helenos/boot/mips32 |
|---|
comment:2 by , 14 years ago
| Type: | defect → enhancement |
|---|
comment:3 by , 9 years ago
| Description: | modified (diff) |
|---|---|
| Summary: | mips32 and arm32 loaders need to maintain cache coherence → mips32 loaders need to maintain cache coherence |
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After the recent unification of the unpacking code, implementing this in boot loader is reduced to just implementing the clearing code and passing it to
extract_payload().