Changeset f9a56c0 in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2006-08-17T11:39:38Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
ee289cf0
Parents:
ec2c55a
Message:

sparc64 work.
interrupt_vector trap experimental handling.
Minimal reverse-engineered FireHose Controller driver (documentation needed!).
Keyboard on Sun Enterprise is now interrupt driven. Keyboard on Sun Ultra
is still polled.

Location:
kernel/arch/sparc64/include
Files:
1 added
5 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/asm.h

    rec2c55a rf9a56c0  
    140140}
    141141
     142/** Write SET_SOFTINT Register.
     143 *
     144 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
     145 *
     146 * @param v New value of SET_SOFTINT register.
     147 */
     148static inline void set_softint_write(uint64_t v)
     149{
     150        __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
     151}
     152
    142153/** Enable interrupts.
    143154 *

  • kernel/arch/sparc64/include/drivers/ns16550.h

    rec2c55a rf9a56c0  
    4040
    4141#define RBR_REG         0       /** Receiver Buffer Register. */
     42#define IER_REG         1       /** Interrupt Enable Register. */
    4243#define LSR_REG         5       /** Line Status Register. */
    4344
    … …  
    4546{
    4647        return kbd_virt_address[RBR_REG];
     48}
     49
     50static inline uint8_t ns16550_ier_read(void)
     51{
     52        return kbd_virt_address[IER_REG];
     53}
     54
     55static inline void ns16550_ier_write(uint8_t v)
     56{
     57        kbd_virt_address[IER_REG] = v;
    4758}
    4859

  • kernel/arch/sparc64/include/drivers/z8530.h

    rec2c55a rf9a56c0  
    7171#define RR15    15
    7272
     73/* Write Register 0 */
     74#define WR0_ERR_RST     (0x6<<3)
     75
    7376/* Write Register 1 */
    7477#define WR1_RID         (0x0<<3)        /** Receive Interrupts Disabled. */

  • kernel/arch/sparc64/include/mm/mmu.h

    rec2c55a rf9a56c0  
    3636#define __sparc64_MMU_H__
    3737
    38 /** LSU Control Register ASI. */
     38/* LSU Control Register ASI. */
    3939#define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
    4040
    41 /** I-MMU ASIs. */
     41/* I-MMU ASIs. */
    4242#define ASI_IMMU                        0x50
    4343#define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    … …  
    4848#define ASI_IMMU_DEMAP                  0x57
    4949
    50 /** Virtual Addresses within ASI_IMMU. */
     50/* Virtual Addresses within ASI_IMMU. */
    5151#define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
    5252#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    … …  
    5454#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    5555
    56 /** D-MMU ASIs. */
     56/* D-MMU ASIs. */
    5757#define ASI_DMMU                        0x58
    5858#define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    … …  
    6464#define ASI_DMMU_DEMAP                  0x5f
    6565
    66 /** Virtual Addresses within ASI_DMMU. */
     66/* Virtual Addresses within ASI_DMMU. */
    6767#define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
    6868#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */

  • kernel/arch/sparc64/include/trap/interrupt.h

    rec2c55a rf9a56c0  
    4141#include <arch/stack.h>
    4242
     43/* Interrupt ASI registers. */
     44#define ASI_UDB_INTR_W                  0x77
     45#define ASI_INTR_DISPATCH_STATUS        0x48
     46#define ASI_UDB_INTR_R                  0x7f
     47#define ASI_INTR_RECEIVE                0x49
     48
     49/* VA's used with ASI_UDB_INTR_W register. */
     50#define ASI_UDB_INTR_W_DATA_0   0x40
     51#define ASI_UDB_INTR_W_DATA_1   0x50
     52#define ASI_UDB_INTR_W_DATA_2   0x60
     53
     54/* VA's used with ASI_UDB_INTR_R register. */
     55#define ASI_UDB_INTR_R_DATA_0   0x40
     56#define ASI_UDB_INTR_R_DATA_1   0x50
     57#define ASI_UDB_INTR_R_DATA_2   0x60
     58
    4359#define TT_INTERRUPT_LEVEL_1                    0x41
    4460#define TT_INTERRUPT_LEVEL_2                    0x42
    … …  
    7187
    7288.macro INTERRUPT_VECTOR_TRAP_HANDLER
     89        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
     90        SIMPLE_HANDLER interrupt
     91        restore
    7392        retry
    7493.endm
    7594#endif /* __ASM__ */
     95
     96#ifndef __ASM__
     97extern void interrupt(void);
     98#endif /* !def __ASM__ */
    7699
    77100#endif
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