Changeset f9a56c0 in mainline for kernel/arch/sparc64/include
- Timestamp:
- 2006-08-17T11:39:38Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- ee289cf0
- Parents:
- ec2c55a
- Location:
- kernel/arch/sparc64/include
- Files:
-
- 1 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/asm.h
rec2c55a rf9a56c0 140 140 } 141 141 142 /** Write SET_SOFTINT Register. 143 * 144 * Bits set in SET_SOFTINT register will be set in SOFTINT register. 145 * 146 * @param v New value of SET_SOFTINT register. 147 */ 148 static inline void set_softint_write(uint64_t v) 149 { 150 __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); 151 } 152 142 153 /** Enable interrupts. 143 154 * -
kernel/arch/sparc64/include/drivers/ns16550.h
rec2c55a rf9a56c0 40 40 41 41 #define RBR_REG 0 /** Receiver Buffer Register. */ 42 #define IER_REG 1 /** Interrupt Enable Register. */ 42 43 #define LSR_REG 5 /** Line Status Register. */ 43 44 … … 45 46 { 46 47 return kbd_virt_address[RBR_REG]; 48 } 49 50 static inline uint8_t ns16550_ier_read(void) 51 { 52 return kbd_virt_address[IER_REG]; 53 } 54 55 static inline void ns16550_ier_write(uint8_t v) 56 { 57 kbd_virt_address[IER_REG] = v; 47 58 } 48 59 -
kernel/arch/sparc64/include/drivers/z8530.h
rec2c55a rf9a56c0 71 71 #define RR15 15 72 72 73 /* Write Register 0 */ 74 #define WR0_ERR_RST (0x6<<3) 75 73 76 /* Write Register 1 */ 74 77 #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ -
kernel/arch/sparc64/include/mm/mmu.h
rec2c55a rf9a56c0 36 36 #define __sparc64_MMU_H__ 37 37 38 /* *LSU Control Register ASI. */38 /* LSU Control Register ASI. */ 39 39 #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ 40 40 41 /* *I-MMU ASIs. */41 /* I-MMU ASIs. */ 42 42 #define ASI_IMMU 0x50 43 43 #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 … … 48 48 #define ASI_IMMU_DEMAP 0x57 49 49 50 /* *Virtual Addresses within ASI_IMMU. */50 /* Virtual Addresses within ASI_IMMU. */ 51 51 #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ 52 52 #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ … … 54 54 #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ 55 55 56 /* *D-MMU ASIs. */56 /* D-MMU ASIs. */ 57 57 #define ASI_DMMU 0x58 58 58 #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 … … 64 64 #define ASI_DMMU_DEMAP 0x5f 65 65 66 /* *Virtual Addresses within ASI_DMMU. */66 /* Virtual Addresses within ASI_DMMU. */ 67 67 #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ 68 68 #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ -
kernel/arch/sparc64/include/trap/interrupt.h
rec2c55a rf9a56c0 41 41 #include <arch/stack.h> 42 42 43 /* Interrupt ASI registers. */ 44 #define ASI_UDB_INTR_W 0x77 45 #define ASI_INTR_DISPATCH_STATUS 0x48 46 #define ASI_UDB_INTR_R 0x7f 47 #define ASI_INTR_RECEIVE 0x49 48 49 /* VA's used with ASI_UDB_INTR_W register. */ 50 #define ASI_UDB_INTR_W_DATA_0 0x40 51 #define ASI_UDB_INTR_W_DATA_1 0x50 52 #define ASI_UDB_INTR_W_DATA_2 0x60 53 54 /* VA's used with ASI_UDB_INTR_R register. */ 55 #define ASI_UDB_INTR_R_DATA_0 0x40 56 #define ASI_UDB_INTR_R_DATA_1 0x50 57 #define ASI_UDB_INTR_R_DATA_2 0x60 58 43 59 #define TT_INTERRUPT_LEVEL_1 0x41 44 60 #define TT_INTERRUPT_LEVEL_2 0x42 … … 71 87 72 88 .macro INTERRUPT_VECTOR_TRAP_HANDLER 89 save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp 90 SIMPLE_HANDLER interrupt 91 restore 73 92 retry 74 93 .endm 75 94 #endif /* __ASM__ */ 95 96 #ifndef __ASM__ 97 extern void interrupt(void); 98 #endif /* !def __ASM__ */ 76 99 77 100 #endif
Note:
See TracChangeset
for help on using the changeset viewer.