| 1 | /*
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| 2 | * Copyright (C) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup sparc64interrupt
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| 30 | * @{
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| 31 | */
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| 32 | /**
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| 33 | * @file
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| 34 | * @brief This file contains interrupt vector trap handler.
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| 35 | */
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| 36 |
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| 37 | #ifndef __sparc64_TRAP_INTERRUPT_H__
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| 38 | #define __sparc64_TRAP_INTERRUPT_H__
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| 39 |
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| 40 | #include <arch/trap/trap_table.h>
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| 41 | #include <arch/stack.h>
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| 42 |
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| 43 | /* Interrupt ASI registers. */
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| 44 | #define ASI_UDB_INTR_W 0x77
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| 45 | #define ASI_INTR_DISPATCH_STATUS 0x48
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| 46 | #define ASI_UDB_INTR_R 0x7f
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| 47 | #define ASI_INTR_RECEIVE 0x49
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| 48 |
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| 49 | /* VA's used with ASI_UDB_INTR_W register. */
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| 50 | #define ASI_UDB_INTR_W_DATA_0 0x40
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| 51 | #define ASI_UDB_INTR_W_DATA_1 0x50
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| 52 | #define ASI_UDB_INTR_W_DATA_2 0x60
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| 53 |
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| 54 | /* VA's used with ASI_UDB_INTR_R register. */
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| 55 | #define ASI_UDB_INTR_R_DATA_0 0x40
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| 56 | #define ASI_UDB_INTR_R_DATA_1 0x50
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| 57 | #define ASI_UDB_INTR_R_DATA_2 0x60
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| 58 |
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| 59 | #define TT_INTERRUPT_LEVEL_1 0x41
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| 60 | #define TT_INTERRUPT_LEVEL_2 0x42
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| 61 | #define TT_INTERRUPT_LEVEL_3 0x43
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| 62 | #define TT_INTERRUPT_LEVEL_4 0x44
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| 63 | #define TT_INTERRUPT_LEVEL_5 0x45
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| 64 | #define TT_INTERRUPT_LEVEL_6 0x46
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| 65 | #define TT_INTERRUPT_LEVEL_7 0x47
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| 66 | #define TT_INTERRUPT_LEVEL_8 0x48
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| 67 | #define TT_INTERRUPT_LEVEL_9 0x49
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| 68 | #define TT_INTERRUPT_LEVEL_10 0x4a
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| 69 | #define TT_INTERRUPT_LEVEL_11 0x4b
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| 70 | #define TT_INTERRUPT_LEVEL_12 0x4c
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| 71 | #define TT_INTERRUPT_LEVEL_13 0x4d
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| 72 | #define TT_INTERRUPT_LEVEL_14 0x4e
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| 73 | #define TT_INTERRUPT_LEVEL_15 0x4f
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| 74 |
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| 75 | #define TT_INTERRUPT_VECTOR_TRAP 0x60
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| 76 |
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| 77 | #define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
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| 78 | #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
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| 79 |
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| 80 | #ifdef __ASM__
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| 81 | .macro INTERRUPT_LEVEL_N_HANDLER n
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| 82 | save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
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| 83 | mov \n - 1, %o0
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| 84 | mov %fp, %o1
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| 85 | PREEMPTIBLE_HANDLER exc_dispatch
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| 86 | .endm
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| 87 |
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| 88 | .macro INTERRUPT_VECTOR_TRAP_HANDLER
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| 89 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
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| 90 | SIMPLE_HANDLER interrupt
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| 91 | restore
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| 92 | retry
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| 93 | .endm
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| 94 | #endif /* __ASM__ */
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| 95 |
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| 96 | #ifndef __ASM__
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| 97 | extern void interrupt(void);
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| 98 | #endif /* !def __ASM__ */
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| 99 |
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| 100 | #endif
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| 101 |
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| 102 | /** @}
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| 103 | */
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