Changeset f619ec11 in mainline for kernel/arch
- Timestamp:
- 2007-02-03T21:26:54Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- cf5ddf6
- Parents:
- 80bcaed
- Location:
- kernel/arch
- Files:
-
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/src/drivers/i8254.c
r80bcaed rf619ec11 69 69 static void i8254_irq_handler(irq_t *irq, void *arg, ...) 70 70 { 71 /* 72 * This IRQ is responsible for kernel preemption. 73 * Nevertheless, we are now holding a spinlock which prevents 74 * preemption. For this particular IRQ, we don't need the 75 * lock. We just release it, call clock() and then reacquire it again. 76 */ 77 spinlock_unlock(&irq->lock); 71 78 clock(); 79 spinlock_lock(&irq->lock); 72 80 } 73 81 … … 137 145 o2 |= inb(CLK_PORT1) << 8; 138 146 139 CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); 147 CPU->delay_loop_const = 148 ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + 149 (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); 140 150 141 151 clk1 = get_cycle(); -
kernel/arch/ia32/src/drivers/i8259.c
r80bcaed rf619ec11 87 87 88 88 pic_disable_irqs(0xffff); /* disable all irq's */ 89 pic_enable_irqs(1 <<IRQ_PIC1); /* but enable pic1 */89 pic_enable_irqs(1 << IRQ_PIC1); /* but enable pic1 */ 90 90 } 91 91 … … 120 120 void pic_eoi(void) 121 121 { 122 outb(0x20, 0x20);123 outb(0xa0, 0x20);122 outb(0x20, 0x20); 123 outb(0xa0, 0x20); 124 124 } 125 125 -
kernel/arch/ia32/src/ia32.c
r80bcaed rf619ec11 119 119 memory_print_map(); 120 120 121 121 #ifdef CONFIG_SMP 122 122 acpi_init(); 123 123 #endif /* CONFIG_SMP */ 124 124 } 125 125 } -
kernel/arch/ia32/src/interrupt.c
r80bcaed rf619ec11 141 141 { 142 142 uint32_t mxcsr; 143 asm 144 ( 143 asm ( 145 144 "stmxcsr %0;\n" 146 145 :"=m"(mxcsr) 147 146 ); 148 147 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", 149 148 (unative_t)mxcsr); 150 149 151 150 decode_istate(istate); -
kernel/arch/ia32/src/smp/smp.c
r80bcaed rf619ec11 113 113 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot() 114 114 */ 115 *((uint16_t *) (PA2KA(0x467 +0))) = ((uintptr_t) ap_boot) >> 4; /* segment */116 *((uint16_t *) (PA2KA(0x467 +2))) = 0; /* offset */115 *((uint16_t *) (PA2KA(0x467 + 0))) = ((uintptr_t) ap_boot) >> 4; /* segment */ 116 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ 117 117 118 118 /* … … 120 120 * BIOS will not do the POST after the INIT signal. 121 121 */ 122 outb(0x70, 0xf);123 outb(0x71, 0xa);122 outb(0x70, 0xf); 123 outb(0x71, 0xa); 124 124 125 125 pic_disable_irqs(0xffff); -
kernel/arch/ia32xen/src/ia32xen.c
r80bcaed rf619ec11 163 163 memory_print_map(); 164 164 165 165 #ifdef CONFIG_SMP 166 166 acpi_init(); 167 167 #endif /* CONFIG_SMP */ 168 168 } 169 169 } -
kernel/arch/ia32xen/src/smp/apic.c
r80bcaed rf619ec11 152 152 */ 153 153 idreg.value = io_apic_read(IOAPICID); 154 if ((1 <<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */154 if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ 155 155 for (i = 0; i < APIC_ID_COUNT; i++) { 156 156 if (!((1<<i) & apic_id_mask)) { … … 303 303 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. 304 304 */ 305 for (i = 0; i <2; i++) {305 for (i = 0; i < 2; i++) { 306 306 icr.lo = l_apic[ICRlo]; 307 307 icr.delmod = DELMOD_STARTUP; … … 402 402 /* Program Logical Destination Register. */ 403 403 ldr.value = l_apic[LDR]; 404 if (CPU->id < sizeof(CPU->id) *8) /* size in bits */405 ldr.id = (1 <<CPU->id);404 if (CPU->id < sizeof(CPU->id) * 8) /* size in bits */ 405 ldr.id = (1 << CPU->id); 406 406 l_apic[LDR] = ldr.value; 407 407 … … 508 508 dlvr = DELMOD_LOWPRI; 509 509 510 reg.lo = io_apic_read(IOREDTBL + pin *2);511 reg.hi = io_apic_read(IOREDTBL + pin *2 + 1);510 reg.lo = io_apic_read(IOREDTBL + pin * 2); 511 reg.hi = io_apic_read(IOREDTBL + pin * 2 + 1); 512 512 513 513 reg.dest = dest; … … 518 518 reg.intvec = v; 519 519 520 io_apic_write(IOREDTBL + pin *2, reg.lo);521 io_apic_write(IOREDTBL + pin *2 + 1, reg.hi);520 io_apic_write(IOREDTBL + pin * 2, reg.lo); 521 io_apic_write(IOREDTBL + pin * 2 + 1, reg.hi); 522 522 } 523 523 … … 540 540 pin = smp_irq_to_pin(i); 541 541 if (pin != -1) { 542 reg.lo = io_apic_read(IOREDTBL + pin *2);542 reg.lo = io_apic_read(IOREDTBL + pin * 2); 543 543 reg.masked = true; 544 544 io_apic_write(IOREDTBL + pin*2, reg.lo); … … 567 567 pin = smp_irq_to_pin(i); 568 568 if (pin != -1) { 569 reg.lo = io_apic_read(IOREDTBL + pin *2);569 reg.lo = io_apic_read(IOREDTBL + pin * 2); 570 570 reg.masked = false; 571 571 io_apic_write(IOREDTBL + pin*2, reg.lo); -
kernel/arch/ia64/src/drivers/it.c
r80bcaed rf619ec11 114 114 itm_write(m); 115 115 srlz_d(); /* propagate changes */ 116 116 117 /* 118 * We are holding a lock which prevents preemption. 119 * Release the lock, call clock() and reacquire the lock again. 120 */ 121 spinlock_unlock(&irq->lock); 117 122 clock(); 123 spinlock_lock(&irq->lock); 118 124 } 119 125 -
kernel/arch/ia64/src/ia64.c
r80bcaed rf619ec11 82 82 83 83 } 84 85 86 84 87 85 void arch_post_mm_init(void) -
kernel/arch/mips32/src/interrupt.c
r80bcaed rf619ec11 114 114 nextcount = cp0_count_read() + cp0_compare_value - drift; 115 115 cp0_compare_write(nextcount); 116 117 /* 118 * We are holding a lock which prevents preemption. 119 * Release the lock, call clock() and reacquire the lock again. 120 */ 121 spinlock_unlock(&irq->lock); 116 122 clock(); 123 spinlock_lock(&irq->lock); 117 124 118 125 if (virtual_timer_fnc != NULL) -
kernel/arch/sparc64/src/drivers/tick.c
r80bcaed rf619ec11 100 100 CPU->missed_clock_ticks++; 101 101 } 102 CPU->arch.next_tick_cmpr = tick_read() + (CPU->arch.clock_frequency /103 102 CPU->arch.next_tick_cmpr = tick_read() + 103 (CPU->arch.clock_frequency / HZ) - drift; 104 104 tick_compare_write(CPU->arch.next_tick_cmpr); 105 105 clock(); -
kernel/arch/sparc64/src/sparc64.c
r80bcaed rf619ec11 137 137 { 138 138 uint64_t stop = tick_read() + (uint64_t) usec * (uint64_t) 139 139 CPU->arch.clock_frequency / 1000000; 140 140 141 141 while (tick_read() < stop) … … 147 147 { 148 148 switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry, 149 150 151 149 ((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE 150 - (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS), 151 (uintptr_t) kernel_uarg->uspace_uarg); 152 152 153 153 for (;;)
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