Changeset f47fd19 in mainline for kernel/arch/sparc64/src

Timestamp:

2006-08-21T13:36:34Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a7961271

Parents:

ee289cf0

Message:

sparc64 work.
Define the istate structure.
Move the identity-mapping handler to assembly.
Make the preemptible handler more general so that TL=1 MMU exceptions can make use of it.

Little bit of formatting and indentation.

Location:

kernel/arch/sparc64/src

Files:

• mm/tlb.c (modified) (4 diffs)
• trap/trap_table.S (modified) (7 diffs)

kernel/arch/sparc64/src/mm/tlb.c

@@ -35 +35 @@
 #include <arch/mm/tlb.h>
 #include <mm/tlb.h>
+#include <mm/as.h>
+#include <mm/asid.h>
 #include <arch/mm/frame.h>
 #include <arch/mm/page.h>
 #include <arch/mm/mmu.h>
-#include <mm/asid.h>
+#include <arch/interrupt.h>
+#include <arch.h>
 #include <print.h>
 #include <arch/types.h>
@@ -47 +50 @@
 #include <arch/asm.h>
 #include <symtab.h>
+
+static void dtlb_pte_copy(pte_t *t);
+static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str);
 
 char *context_encoding[] = {
@@ -100 +106 @@
 }
 
+void dtlb_pte_copy(pte_t *t)
+{
+}
+
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(void)
+void fast_instruction_access_mmu_miss(int n, istate_t *istate)
 {
         panic("%s\n", __FUNCTION__);
 }
 
-/** DTLB miss handler. */
-void fast_data_access_mmu_miss(void)
+/** DTLB miss handler.
+ *
+ * Note that some faults (e.g. kernel faults) were already resolved
+ * by the low-level, assembly language part of the fast_data_access_mmu_miss
+ * handler.
+ */
+void fast_data_access_mmu_miss(int n, istate_t *istate)
 {
         tlb_tag_access_reg_t tag;
-        uintptr_t tpc;
-        char *tpc_str;
+        uintptr_t va;
+        pte_t *t;
 
         tag.value = dtlb_tag_access_read();
-        if (tag.context != ASID_KERNEL || tag.vpn == 0) {
-                tpc = tpc_read();
-                tpc_str = get_symtab_entry(tpc);
-
-                printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
-                printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
-                panic("%s\n", __FUNCTION__);
-        }
-
-        /*
-         * Identity map piece of faulting kernel address space.
-         */
-        dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
+        va = tag.vpn * PAGE_SIZE;
+        if (tag.context == ASID_KERNEL) {
+                if (!tag.vpn) {
+                        /* NULL access in kernel */
+                        do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
+                }
+                do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault.");
+        }
+
+        page_table_lock(AS, true);
+        t = page_mapping_find(AS, va);
+        if (t) {
+                /*
+                 * The mapping was found in the software page hash table.
+                 * Insert it into DTLB.
+                 */
+                dtlb_pte_copy(t);
+                page_table_unlock(AS, true);
+        } else {
+                /*
+                 * Forward the page fault to the address space page fault handler.
+                 */             
+                page_table_unlock(AS, true);
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
+                }
+        }
 }
 
 /** DTLB protection fault handler. */
-void fast_data_access_protection(void)
+void fast_data_access_protection(int n, istate_t *istate)
 {
         panic("%s\n", __FUNCTION__);
@@ -162 +191 @@
 }
 
+void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str)
+{
+        tlb_tag_access_reg_t tag;
+        uintptr_t va;
+        char *tpc_str = get_symtab_entry(istate->tpc);
+
+        tag.value = dtlb_tag_access_read();
+        va = tag.vpn * PAGE_SIZE;
+
+        printf("Faulting page: %p, ASID=%d\n", va, tag.context);
+        printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
+        panic("%s\n", str);
+}
+
 /** Invalidate all unlocked ITLB and DTLB entries. */
 void tlb_invalidate_all(void)

kernel/arch/sparc64/src/trap/trap_table.S

@@ -44 +44 @@
 #include <arch/trap/mmu.h>
 #include <arch/stack.h>
+#include <arch/regdef.h>
 
 #define TABLE_SIZE      TRAP_TABLE_SIZE
@@ -276 +277 @@
 
 
-/* Preemptible trap handler.
- *
- * This trap handler makes arrangements to
- * make calling scheduler() possible.
- *
- * The caller is responsible for doing save
- * and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE
- * bytes on stack.
+/* Preemptible trap handler for TL=1.
+ *
+ * This trap handler makes arrangements to make calling of scheduler() from
+ * within a trap context possible. It is guaranteed to function only when traps
+ * are not nested (i.e. for TL=1).
+ *
+ * Every trap handler on TL=1 that makes a call to the scheduler needs to
+ * be based on this function. The reason behind it is that the nested
+ * trap levels and the automatic saving of the interrupted context by hardware
+ * does not work well together with scheduling (i.e. a thread cannot be rescheduled
+ * with TL>0). Therefore it is necessary to eliminate the effect of trap levels
+ * by software and save the necessary state on the kernel stack.
+ *
+ * Note that for traps with TL>1, more state needs to be saved. This function
+ * is therefore not going to work when TL>1.
+ *
+ * The caller is responsible for doing SAVE and allocating
+ * PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE bytes on the stack.
  *
  * Input registers:
@@ -300 +311 @@
         rdpr %pstate, %g4
 
+        /*
+         * The following memory accesses will not fault
+         * because special provisions are made to have
+         * the kernel stack of THREAD locked in DTLB.
+         */
         stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
         stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
@@ -314 +330 @@
          * - switch to normal globals.
          */
-        and %g4, ~1, %g4                ! mask alternate globals
+        and %g4, ~(PSTATE_AG_BIT|PSTATE_IG_BIT|PSTATE_MG_BIT), %g4
         wrpr %g4, 0, %pstate
          
@@ -325 +341 @@
          * Call the higher-level handler.
          */
+        mov %fp, %o1                            ! calculate istate address
         call %l0
-        nop
-        
-        /*
-         * Restore the normal global register set.
+        add %o1, STACK_BIAS + SAVED_PSTATE, %o1 ! calculate istate address
+        
+        /*
+         * Restore       the normal global register set.
          */
         RESTORE_GLOBALS
@@ -335 +352 @@
         /*
          * Restore PSTATE from saved copy.
-         * Alternate globals become active.
+         * Alternate/Interrupt/MM globals become active.
          */
         ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
@@ -358 +375 @@
 
         /*
-         * On execution of retry instruction, CWP will be restored from TSTATE register.
-         * However, because of scheduling, it is possible that CWP in saved TSTATE
-         * is different from current CWP. The following chunk of code fixes CWP
-         * in the saved copy of TSTATE.
+         * On execution of the RETRY instruction, CWP will be restored from the TSTATE
+         * register. However, because of scheduling, it is possible that CWP in the saved
+         * TSTATE is different from the current CWP. The following chunk of code fixes
+         * CWP in the saved copy of TSTATE.
          */
         rdpr %cwp, %g4          ! read current CWP