Changeset f24d300 in mainline for kernel/arch/amd64/include/atomic.h

Timestamp:

2009-03-03T15:52:55Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e762b43

Parents:

add04f7

Message:

better inline assembler readability using the new symbolic syntax

File:

• kernel/arch/amd64/include/atomic.h (modified) (9 diffs)

kernel/arch/amd64/include/atomic.h

@@ -27 +27 @@
  */
 
-/** @addtogroup amd64   
+/** @addtogroup amd64
  * @{
  */
@@ -42 +42 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-        asm volatile ("lock incq %0\n" : "+m" (val->count));
+        asm volatile (
+                "lock incq %[count]\n"
+                : [count] "+m" (val->count)
+        );
 #else
-        asm volatile ("incq %0\n" : "+m" (val->count));
+        asm volatile (
+                "incq %[count]\n"
+                : [count] "+m" (val->count)
+        );
 #endif /* CONFIG_SMP */
 }
@@ -50 +56 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-        asm volatile ("lock decq %0\n" : "+m" (val->count));
+        asm volatile (
+                "lock decq %[count]\n"
+                : [count] "+m" (val->count)
+        );
 #else
-        asm volatile ("decq %0\n" : "+m" (val->count));
+        asm volatile (
+                "decq %[count]\n"
+                : [count] "+m" (val->count)
+        );
 #endif /* CONFIG_SMP */
 }
@@ -59 +71 @@
 {
         long r = 1;
-
+        
         asm volatile (
-                "lock xaddq %1, %0\n"
-                : "+m" (val->count), "+r" (r)
+                "lock xaddq %[r], %[count]\n"
+                : [count] "+m" (val->count), [r] "+r" (r)
         );
-
+        
         return r;
 }
@@ -73 +85 @@
         
         asm volatile (
-                "lock xaddq %1, %0\n"
-                : "+m" (val->count), "+r" (r)
+                "lock xaddq %[r], %[count]\n"
+                : [count] "+m" (val->count), [r] "+r" (r)
         );
         
@@ -80 +92 @@
 }
 
-#define atomic_preinc(val) (atomic_postinc(val) + 1)
-#define atomic_predec(val) (atomic_postdec(val) - 1)
+#define atomic_preinc(val)  (atomic_postinc(val) + 1)
+#define atomic_predec(val)  (atomic_postdec(val) - 1)
 
 static inline uint64_t test_and_set(atomic_t *val) {
@@ -87 +99 @@
         
         asm volatile (
-                "movq $1, %0\n"
-                "xchgq %0, %1\n"
-                : "=r" (v), "+m" (val->count)
+                "movq $1, %[v]\n"
+                "xchgq %[v], %[count]\n"
+                : [v] "=r" (v), [count] "+m" (val->count)
         );
         
@@ -100 +112 @@
 {
         uint64_t tmp;
-
+        
         preemption_disable();
         asm volatile (
@@ -107 +119 @@
                 "pause\n"
 #endif
-                "mov %0, %1\n"
-                "testq %1, %1\n"
+                "mov %[count], %[tmp]\n"
+                "testq %[tmp], %[tmp]\n"
                 "jnz 0b\n"       /* lightweight looping on locked spinlock */
                 
-                "incq %1\n"      /* now use the atomic operation */
-                "xchgq %0, %1\n"
-                "testq %1, %1\n"
+                "incq %[tmp]\n"  /* now use the atomic operation */
+                "xchgq %[count], %[tmp]\n"
+                "testq %[tmp], %[tmp]\n"
                 "jnz 0b\n"
-                : "+m" (val->count), "=&r" (tmp)
+                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
         );
         /*