Changeset edebc15c in mainline for kernel/arch/mips32/include

Timestamp:

2008-07-27T03:50:53Z (17 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4541ae4

Parents:

5e8ddf5

Message:

physical memory detection in MSIM (discontinous regions supported)
remove Sgi Indy (ARC) support — it was unmaintaned, untested for years and without uspace support

Location:

kernel/arch/mips32/include

Files:

• drivers/arc.h (deleted)
• drivers/msim.h (modified) (1 diff)
• drivers/serial.h (modified) (2 diffs)
• mm/as.h (modified) (1 diff)
• mm/tlb.h (modified) (3 diffs)

kernel/arch/mips32/include/drivers/msim.h

@@ -36 +36 @@
 #define KERN_mips32_MSIM_H_
 
+/** Address of devices. */
+#define MSIM_VIDEORAM           0xB0000000
+#define MSIM_KBD_ADDRESS        0xB0000000
+#define MSIM_KBD_IRQ            2
+
 #include <console/chardev.h>
 

kernel/arch/mips32/include/drivers/serial.h

@@ -38 +38 @@
 #include <console/chardev.h>
 
+#define SERIAL_ADDRESS    0xB8000000
+
 #define SERIAL_MAX        4
 #define SERIAL_COM1       0x3f8
@@ -44 +46 @@
 #define SERIAL_COM2_IRQ   3
 
-#define P_WRITEB(where,what)     (*((volatile char *) (0xB8000000+where))=what)
-#define P_READB(where)           (*((volatile char *)(0xB8000000+where)))
+#define P_WRITEB(where, what)     (*((volatile char *) (SERIAL_ADDRESS + where)) = what)
+#define P_READB(where)            (*((volatile char *) (SERIAL_ADDRESS + where)))
 
-#define SERIAL_READ(x)           P_READB(x)
-#define SERIAL_WRITE(x,c)        P_WRITEB(x,c)
+#define SERIAL_READ(x)            P_READB(x)
+#define SERIAL_WRITE(x, c)        P_WRITEB(x, c)
+
 /* Interrupt enable register */
 #define SERIAL_READ_IER(x)              (P_READB((x) + 1))
-#define SERIAL_WRITE_IER(x,c)           (P_WRITEB((x)+1,c))
+#define SERIAL_WRITE_IER(x,c)           (P_WRITEB((x) + 1, c))
+
 /* Interrupt identification register */
 #define SERIAL_READ_IIR(x)             (P_READB((x) + 2))
+
 /* Line status register */
 #define SERIAL_READ_LSR(x)             (P_READB((x) + 5))

kernel/arch/mips32/include/mm/as.h

@@ -39 +39 @@
 
 #define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x80000000
-#define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffff
+#define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0x9fffffff
 #define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x00000000
 #define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0x7fffffff

kernel/arch/mips32/include/mm/tlb.h

@@ -36 +36 @@
 #define KERN_mips32_TLB_H_
 
+#include <arch/types.h>
+#include <typedefs.h>
+#include <arch/mm/asid.h>
 #include <arch/exception.h>
 
@@ -47 +50 @@
 #define TLB_KSTACK_WIRED_INDEX  0
 
-#define TLB_PAGE_MASK_16K       (0x3<<13)
+#define TLB_PAGE_MASK_16K       (0x3 << 13)
 
 #define PAGE_UNCACHED                   2
@@ -160 +163 @@
 extern void tlb_refill(istate_t *istate);
 extern void tlb_modified(istate_t *istate);
+extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
+extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
 #endif