Changeset ec08286 in mainline for kernel/genarch

Timestamp:

2010-07-25T14:35:05Z (15 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

277cf60

Parents:

24697c3

Message:

Kernel input device for gta02 serial console. Move s3c24xx interrupt controller functionality into a separate C file.

Location:

kernel/genarch

Files:

• Makefile.inc (modified) (1 diff)
• include/drivers/s3c24xx_irqc/s3c24xx_irqc.h (modified) (2 diffs)
• include/drivers/s3c24xx_uart/s3c24xx_uart.h (modified) (1 diff)
• src/drivers/s3c24xx_irqc/s3c24xx_irqc.c (added)
• src/drivers/s3c24xx_uart/s3c24xx_uart.c (modified) (6 diffs)

kernel/genarch/Makefile.inc

@@ -90 +90 @@
 endif
 
+ifeq ($(CONFIG_S3C24XX_IRQC),y)
+        GENARCH_SOURCES += \
+                genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c
+endif
+
 ifeq ($(CONFIG_S3C24XX_UART),y)
         GENARCH_SOURCES += \

kernel/genarch/include/drivers/s3c24xx_irqc/s3c24xx_irqc.h

@@ -53 +53 @@
         ioport32_t subsrcpnd;   /**< Sub source pending */
         ioport32_t intsubmsk;   /** Interrupt sub mask */
-} s3c24xx_irqc_t;
+} s3c24xx_irqc_regs_t;
 
 /** S3C24xx Interrupt source numbers.
@@ -120 +120 @@
 #define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource))
 
+typedef struct {
+        s3c24xx_irqc_regs_t *regs;
+} s3c24xx_irqc_t;
+
+extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *);
+extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *);
+extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned);
+extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned);
+
 #endif
 

kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h

@@ -38 +38 @@
 #define KERN_S3C24XX_UART_H_
 
+#include <ddi/irq.h>
+#include <console/chardev.h>
 #include <typedefs.h>
-#include <console/chardev.h>
 
-extern outdev_t *s3c24xx_uart_init(ioport8_t *);
+typedef struct {
+        ioport8_t *base;
+        indev_t *indev;
+        irq_t irq;
+} s3c24xx_uart_instance_t;
+
+extern outdev_t *s3c24xx_uart_init(ioport8_t *, inr_t inr);
+extern void s3c24xx_uart_input_wire(s3c24xx_uart_instance_t *,
+    indev_t *);
 
 #endif

kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

@@ -40 +40 @@
 #include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
 #include <console/chardev.h>
+#include <console/console.h>
+#include <ddi/device.h>
 #include <arch/asm.h>
 #include <mm/slab.h>
-#include <console/console.h>
 #include <sysinfo/sysinfo.h>
 #include <str.h>
 
 /** S3C24xx UART register offsets */
-#define S3C24XX_UTRSTAT         0x10
-#define S3C24XX_UTXH            0x20
+#define S3C24XX_ULCON                   0x00
+#define S3C24XX_UCON                    0x04
+#define S3C24XX_UFCON                   0x08
+#define S3C24XX_UMCON                   0x0c
+#define S3C24XX_UTRSTAT                 0x10
+#define S3C24XX_UERSTAT                 0x14
+#define S3C24XX_UFSTAT                  0x18
+#define S3C24XX_UMSTAT                  0x1c
+#define S3C24XX_UTXH                    0x20
+#define S3C24XX_URXH                    0x24
+#define S3C24XX_UBRDIV                  0x28
 
-/* Bits in UTXH register */
-#define S3C24XX_UTXH_TX_EMPTY   0x4
-
-typedef struct {
-        ioport8_t *base;
-} s3c24xx_uart_instance_t;
+/* Bits in UTRSTAT register */
+#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
+#define S3C24XX_UTRSTAT_RDATA           0x1
 
 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
@@ -67 +74 @@
 
         /* Wait for transmitter to be empty. */
-        while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0)
+        while ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
                 ;
 
@@ -86 +93 @@
 }
 
+static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
+{
+        return IRQ_ACCEPT;
+}
+
+static void s3c24xx_uart_irq_handler(irq_t *irq)
+{
+        s3c24xx_uart_instance_t *instance = irq->instance;
+        ioport32_t *utrstat, *urxh;
+
+        utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT);
+        urxh = (ioport32_t *) (instance->base + S3C24XX_URXH);
+
+        if ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
+                uint32_t data = pio_read_32(urxh);
+                indev_push_character(instance->indev, data & 0xff);
+        }
+}
+
 static outdev_operations_t s3c24xx_uart_ops = {
         .write = s3c24xx_uart_putchar,
@@ -91 +117 @@
 };
 
-outdev_t *s3c24xx_uart_init(ioport8_t *base)
+outdev_t *s3c24xx_uart_init(ioport8_t *base, inr_t inr)
 {
         outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
@@ -108 +134 @@
 
         instance->base = base;
+        instance->indev = NULL;
+
+        /* Initialize IRQ structure. */
+        irq_initialize(&instance->irq);
+        instance->irq.devno = device_assign_devno();
+        instance->irq.inr = inr;
+        instance->irq.claim = s3c24xx_uart_claim;
+        instance->irq.handler = s3c24xx_uart_irq_handler;
+        instance->irq.instance = instance;
+
+        /* Disable FIFO */
+        ioport32_t *ufcon;
+        ufcon = (ioport32_t *) (instance->base + S3C24XX_UFCON);
+        pio_write_32(ufcon, pio_read_32(ufcon) & ~0x01);
+
+        /* Set RX interrupt to pulse mode */
+        ioport32_t *ucon;
+        ucon = (ioport32_t *) (instance->base + S3C24XX_UCON);
+        pio_write_32(ucon, pio_read_32(ucon) & ~(1 << 8));
 
         if (!fb_exported) {
@@ -124 +169 @@
 }
 
+void s3c24xx_uart_input_wire(s3c24xx_uart_instance_t *instance, indev_t *indev)
+{
+        ASSERT(instance);
+        ASSERT(indev);
+
+        instance->indev = indev;
+        irq_register(&instance->irq);
+}
+
 /** @}
  */