| 1 | /*
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| 2 | * Copyright (c) 2010 Jiri Svoboda
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup genarch
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| 30 | * @{
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| 31 | */
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| 32 | /**
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| 33 | * @file
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| 34 | * @brief Samsung S3C24xx on-chip interrupt controller driver.
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| 35 | */
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| 36 |
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| 37 | #ifndef KERN_S3C24XX_IRQC_H_
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| 38 | #define KERN_S3C24XX_IRQC_H_
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| 39 |
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| 40 | #include <typedefs.h>
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| 41 |
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| 42 | /** Physical address where S3C24XX Interrupt controller is mapped */
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| 43 | #define S3C24XX_IRQC_ADDRESS 0x4a000000
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| 44 |
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| 45 | /** S3C24xx on-chip interrupt controller registers */
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| 46 | typedef struct {
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| 47 | ioport32_t srcpnd; /**< Source pending */
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| 48 | ioport32_t intmod; /**< Interrupt mode */
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| 49 | ioport32_t intmsk; /**< Interrupt mask */
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| 50 | ioport32_t priority; /**< Priority */
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| 51 | ioport32_t intpnd; /**< Interrupt pending */
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| 52 | ioport32_t intoffset; /**< Interrupt offset */
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| 53 | ioport32_t subsrcpnd; /**< Sub source pending */
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| 54 | ioport32_t intsubmsk; /** Interrupt sub mask */
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| 55 | } s3c24xx_irqc_t;
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| 56 |
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| 57 | /** S3C24xx Interrupt source numbers.
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| 58 | *
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| 59 | * These correspond to bit numbers in srcpnd, intmod, intmsk and intpnd
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| 60 | * registers as well as to the values read from the intoffset register.
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| 61 | */
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| 62 | enum s3c24xx_int_source {
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| 63 | S3C24XX_INT_ADC = 31,
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| 64 | S3C24XX_INT_RTC = 30,
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| 65 | S3C24XX_INT_SPI1 = 29,
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| 66 | S3C24XX_INT_UART0 = 28,
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| 67 | S3C24XX_INT_IIC = 27,
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| 68 | S3C24XX_INT_USBH = 26,
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| 69 | S3C24XX_INT_USBD = 25,
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| 70 | S3C24XX_INT_NFCON = 24,
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| 71 | S3C24XX_INT_UART1 = 23,
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| 72 | S3C24XX_INT_SPI0 = 22,
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| 73 | S3C24XX_INT_SDI = 21,
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| 74 | S3C24XX_INT_DMA3 = 20,
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| 75 | S3C24XX_INT_DMA2 = 19,
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| 76 | S3C24XX_INT_DMA1 = 18,
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| 77 | S3C24XX_INT_DMA0 = 17,
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| 78 | S3C24XX_INT_LCD = 16,
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| 79 | S3C24XX_INT_UART2 = 15,
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| 80 | S3C24XX_INT_TIMER4 = 14,
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| 81 | S3C24XX_INT_TIMER3 = 13,
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| 82 | S3C24XX_INT_TIMER2 = 12,
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| 83 | S3C24XX_INT_TIMER1 = 11,
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| 84 | S3C24XX_INT_TIMER0 = 10,
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| 85 | S3C24XX_INT_WDT_AC97 = 9,
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| 86 | S3C24XX_INT_TICK = 8,
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| 87 | S3C24XX_nBATT_FLT = 7,
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| 88 | S3C24XX_INT_CAM = 6,
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| 89 | S3C24XX_EINT8_23 = 5,
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| 90 | S3C24XX_EINT4_7 = 4,
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| 91 | S3C24XX_EINT3 = 3,
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| 92 | S3C24XX_EINT2 = 2,
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| 93 | S3C24XX_EINT1 = 1,
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| 94 | S3C24XX_EINT0 = 0
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| 95 | };
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| 96 |
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| 97 | /** S3C24xx Interrupt sub-source numbers.
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| 98 | *
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| 99 | * These correspond to bit numbers in the intsubmsk register.
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| 100 | */
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| 101 | enum s3c24xx_int_subsource {
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| 102 | S3C24XX_SUBINT_AC97 = 14,
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| 103 | S3C24XX_SUBINT_WDT = 13,
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| 104 | S3C24XX_SUBINT_CAM_P = 12,
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| 105 | S3C24XX_SUBINT_CAM_C = 11,
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| 106 | S3C24XX_SUBINT_ADC_S = 10,
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| 107 | S3C24XX_SUBINT_TC = 9,
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| 108 | S3C24XX_SUBINT_ERR2 = 8,
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| 109 | S3C24XX_SUBINT_TXD2 = 7,
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| 110 | S3C24XX_SUBINT_RXD2 = 6,
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| 111 | S3C24XX_SUBINT_ERR1 = 5,
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| 112 | S3C24XX_SUBINT_TXD1 = 4,
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| 113 | S3C24XX_SUBINT_RXD1 = 3,
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| 114 | S3C24XX_SUBINT_ERR0 = 2,
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| 115 | S3C24XX_SUBINT_TXD0 = 1,
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| 116 | S3C24XX_SUBINT_RXD0 = 0
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| 117 | };
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| 118 |
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| 119 | #define S3C24XX_INT_BIT(source) (1 << (source))
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| 120 | #define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource))
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| 121 |
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| 122 | #endif
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| 123 |
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| 124 | /** @}
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| 125 | */
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