Changeset e386cbf in mainline for kernel/arch/sparc64/include/mm

Timestamp:

2006-08-01T15:58:32Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e12ccc5

Parents:

b3e8c90

Message:

sparc64 work.
Dump take_over_tlb_and_tt() and add its assembly language replacement.

Location:

kernel/arch/sparc64/include/mm

Files:

• mmu.h (modified) (1 diff)
• tlb.h (modified) (6 diffs)
• tte.h (modified) (2 diffs)

kernel/arch/sparc64/include/mm/mmu.h

@@ -104 +104 @@
 typedef union lsu_cr_reg lsu_cr_reg_t;
 
-#endif /* !__ASM__ */
+#endif /* !def __ASM__ */
 
 #endif

kernel/arch/sparc64/include/mm/tlb.h

@@ -36 +36 @@
 #define __sparc64_TLB_H__
 
+
+#define ITLB_ENTRY_COUNT                64
+#define DTLB_ENTRY_COUNT                64
+
+#define MEM_CONTEXT_KERNEL              0
+#define MEM_CONTEXT_TEMP                1
+
+/** Page sizes. */
+#define PAGESIZE_8K     0
+#define PAGESIZE_64K    1
+#define PAGESIZE_512K   2
+#define PAGESIZE_4M     3
+
+/** Bit width of the TLB-locked portion of kernel address space. */
+#define KERNEL_PAGE_WIDTH       22      /* 4M */
+
+/* TLB Demap Operation types. */
+#define TLB_DEMAP_PAGE          0
+#define TLB_DEMAP_CONTEXT       1
+
+#define TLB_DEMAP_TYPE_SHIFT    6
+
+/* TLB Demap Operation Context register encodings. */
+#define TLB_DEMAP_PRIMARY       0
+#define TLB_DEMAP_SECONDARY     1
+#define TLB_DEMAP_NUCLEUS       2
+
+#define TLB_DEMAP_CONTEXT_SHIFT 4
+
+/* TLB Tag Access shifts */
+#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
+#define TLB_TAG_ACCESS_VPN_SHIFT        13
+
+#ifndef __ASM__
+
 #include <arch/mm/tte.h>
 #include <arch/mm/mmu.h>
@@ -43 +78 @@
 #include <arch/types.h>
 #include <typedefs.h>
-
-#define ITLB_ENTRY_COUNT                64
-#define DTLB_ENTRY_COUNT                64
-
-/** Page sizes. */
-#define PAGESIZE_8K     0
-#define PAGESIZE_64K    1
-#define PAGESIZE_512K   2
-#define PAGESIZE_4M     3
-
-/** Bit width of the TLB-locked portion of kernel address space. */
-#define KERNEL_PAGE_WIDTH       22      /* 4M */
 
 union tlb_context_reg {
@@ -91 +114 @@
 typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
-/** TLB Demap Operation types. */
-#define TLB_DEMAP_PAGE          0
-#define TLB_DEMAP_CONTEXT       1
-
-/** TLB Demap Operation Context register encodings. */
-#define TLB_DEMAP_PRIMARY       0
-#define TLB_DEMAP_SECONDARY     1
-#define TLB_DEMAP_NUCLEUS       2
 
 /** TLB Demap Operation Address. */
@@ -385 +400 @@
         da.vpn = pg.vpn;
         
-        asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
+        asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);     /* da.value is the address within the ASI */ 
         flush();
 }
@@ -407 +422 @@
         da.vpn = pg.vpn;
         
-        asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
+        asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ 
         membar();
 }
@@ -417 +432 @@
 extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
+#endif /* !def __ASM__ */
+
 #endif
 

kernel/arch/sparc64/include/mm/tte.h

@@ -35 +35 @@
 #ifndef __sparc64_TTE_H__
 #define __sparc64_TTE_H__
+
+#define TTE_G           (1<<0)
+#define TTE_W           (1<<1)
+#define TTE_P           (1<<2)
+#define TTE_E           (1<<3)
+#define TTE_CV          (1<<4)
+#define TTE_CP          (1<<5)
+#define TTE_L           (1<<6)
+
+#define TTE_V_SHIFT     63
+#define TTE_SIZE_SHIFT  61
+
+#ifndef __ASM__
 
 #include <arch/types.h>
@@ -76 +89 @@
 typedef union tte_data tte_data_t;
 
+#endif /* !def __ASM__ */
+
 #endif