Changeset e2a0d76 in mainline for kernel/arch

Timestamp:

2013-09-09T23:29:57Z (12 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ba2be23

Parents:

8cbf1c3

Message:

cstyle

Location:

kernel/arch

Files:

• arm32/src/ras.c (modified) (1 diff)
• ia64/src/mm/vhpt.c (modified) (1 diff)
• mips32/include/arch/mm/page.h (modified) (3 diffs)
• sparc64/src/mm/sun4u/as.c (modified) (1 diff)
• sparc64/src/mm/sun4v/as.c (modified) (1 diff)

kernel/arch/arm32/src/ras.c

@@ -51 +51 @@
 void ras_init(void)
 {
-        uintptr_t frame;
-
-        frame = frame_alloc(ONE_FRAME,
+        uintptr_t frame = frame_alloc(ONE_FRAME,
             FRAME_ATOMIC | FRAME_HIGHMEM, 0);
         if (!frame)
                 frame = frame_alloc(ONE_FRAME, FRAME_LOWMEM, 0);
+        
         ras_page = (uintptr_t *) km_map(frame,
             PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
-
+        
         memsetb(ras_page, PAGE_SIZE, 0); 
         ras_page[RAS_START] = 0;

kernel/arch/ia64/src/mm/vhpt.c

@@ -46 +46 @@
         if (!vhpt_base)
                 panic("Kernel configured with VHPT but no memory for table.");
+        
         vhpt_invalidate_all();
         return (uintptr_t) vhpt_base;

kernel/arch/mips32/include/arch/mm/page.h

@@ -27 +27 @@
  */
 
-/** @addtogroup mips32mm        
+/** @addtogroup mips32mm
  * @{
  */
@@ -70 +70 @@
  * - PTL3 has 4096 entries (12 bits)
  */
- 
+
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH       64
-#define PTL1_ENTRIES_ARCH       0
-#define PTL2_ENTRIES_ARCH       0
-#define PTL3_ENTRIES_ARCH       4096
+#define PTL0_ENTRIES_ARCH  64
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  4096
 
 /* Macros describing size of page tables in each level. */
@@ -84 +84 @@
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
-#define PTL1_INDEX_ARCH(vaddr)  0
-#define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */ 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
         (((pte_t *) (ptl0))[(i)].pfn << 12)

kernel/arch/sparc64/src/mm/sun4u/as.c

@@ -72 +72 @@
         
         uintptr_t tsb = PA2KA(frame_alloc(order, flags, 0));
-        
         if (!tsb)
                 return -1;

kernel/arch/sparc64/src/mm/sun4v/as.c

@@ -70 +70 @@
         
         uintptr_t tsb = frame_alloc(order, flags, 0);
-        
         if (!tsb)
                 return -1;