Changeset de96d3b in mainline for kernel/arch/amd64

Timestamp:

2024-01-03T16:54:15Z (2 years ago)

Author:

Jiří Zárevúcky <zarevucky.jiri@…>

Branches:

master, topic/simplify-dev-export

Children:

00e6288, 25e1490

Parents:

7130754

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2024-01-01 04:12:52)

git-committer:

Jiří Zárevúcky <zarevucky.jiri@…> (2024-01-03 16:54:15)

Message:

On x86 CPUs supporting it, use write-combining memory mode for framebuffer

With this, kernel printouts are about three times faster in QEMU.

Location:

kernel/arch/amd64

Files:

• include/arch/mm/page.h (modified) (4 diffs)
• include/arch/mm/pat.h (added)
• src/amd64.c (modified) (2 diffs)

kernel/arch/amd64/include/arch/mm/page.h

@@ -192 +192 @@
         unsigned int accessed : 1;
         unsigned int dirty : 1;
-        unsigned int unused : 1;
+        unsigned int pat : 1;
         unsigned int global : 1;
         unsigned int soft_valid : 1;  /**< Valid content even if present bit is cleared. */
@@ -211 +211 @@
             p->writeable << PAGE_WRITE_SHIFT |
             (!p->no_execute) << PAGE_EXEC_SHIFT |
-            p->global << PAGE_GLOBAL_SHIFT);
+            p->global << PAGE_GLOBAL_SHIFT |
+            p->page_write_through << PAGE_WRITE_COMBINE_SHIFT);
 }
 
@@ -225 +226 @@
         pte_t *p = &pt[i];
 
-        p->page_cache_disable = !(flags & PAGE_CACHEABLE);
         p->present = !(flags & PAGE_NOT_PRESENT);
         p->uaccessible = (flags & PAGE_USER) != 0;
@@ -232 +232 @@
         p->global = (flags & PAGE_GLOBAL) != 0;
 
+        if (flags & PAGE_WRITE_COMBINE) {
+                /* We have mapped PCD+PWT bits to write-combine mode via PAT MSR. */
+                /* (If PAT is unsupported, it will default to uncached.) */
+                p->page_cache_disable = 1;
+                p->page_write_through = 1;
+        } else {
+                p->page_cache_disable = !(flags & PAGE_CACHEABLE);
+                p->page_write_through = 0;
+        }
+
         /*
          * Ensure that there is at least one bit set even if the present bit is cleared.

kernel/arch/amd64/src/amd64.c

@@ -60 +60 @@
 #include <arch/vreg.h>
 #include <arch/kseg.h>
+#include <arch/mm/pat.h>
 #include <genarch/pic/pic_ops.h>
 
@@ -115 +116 @@
         /* Disable alignment check */
         write_cr0(read_cr0() & ~CR0_AM);
+
+        /* Use PCD+PWT bit combination in PTE to mean write-combining mode. */
+        if (pat_supported())
+                pat_set_mapping(false, true, true, PAT_TYPE_WRITE_COMBINING);
 
         if (config.cpu_active == 1) {