source: mainline/kernel/arch/amd64/include/arch/mm/page.h@ f114d40

ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f114d40 was f114d40, checked in by Jakub Jermář <jakub@…>, 3 years ago

Change amd64 pte_t bitfields to have a 40-bit address field and 11-bit reserved field.

  • Property mode set to 100644
File size: 7.9 KB
Line 
1/*
2 * Copyright (c) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup kernel_amd64_mm
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_PAGE_H_
36#define KERN_amd64_PAGE_H_
37
38#include <arch/mm/frame.h>
39
40#define PAGE_WIDTH FRAME_WIDTH
41#define PAGE_SIZE FRAME_SIZE
42
43#ifdef MEMORY_MODEL_kernel
44
45#ifndef __ASSEMBLER__
46
47#define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffffffff80000000))
48#define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffffffff80000000))
49
50#else /* __ASSEMBLER__ */
51
52#define KA2PA(x) ((x) - 0xffffffff80000000)
53#define PA2KA(x) ((x) + 0xffffffff80000000)
54
55#endif /* __ASSEMBLER__ */
56
57#endif /* MEMORY_MODEL_kernel */
58
59#ifdef MEMORY_MODEL_large
60
61#ifndef __ASSEMBLER__
62
63#define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
64#define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
65
66#else /* __ASSEMBLER__ */
67
68#define KA2PA(x) ((x) - 0xffff800000000000)
69#define PA2KA(x) ((x) + 0xffff800000000000)
70
71#endif /* __ASSEMBLER__ */
72
73#endif /* MEMORY_MODEL_large */
74
75/* Number of entries in each level. */
76#define PTL0_ENTRIES_ARCH 512
77#define PTL1_ENTRIES_ARCH 512
78#define PTL2_ENTRIES_ARCH 512
79#define PTL3_ENTRIES_ARCH 512
80
81/* Page table sizes for each level. */
82#define PTL0_FRAMES_ARCH 1
83#define PTL1_FRAMES_ARCH 1
84#define PTL2_FRAMES_ARCH 1
85#define PTL3_FRAMES_ARCH 1
86
87/* Macros calculating indices into page tables in each level. */
88#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ffU)
89#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ffU)
90#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ffU)
91#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ffU)
92
93/* Get PTE address accessors for each level. */
94#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
95 ((pte_t *) (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_51) << 12))
96#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
97 ((pte_t *) (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_51) << 12))
98#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
99 ((pte_t *) (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_51) << 12))
100#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
101 ((uintptr_t *) (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_51) << 12))
102
103/* Set PTE address accessors for each level. */
104#define SET_PTL0_ADDRESS_ARCH(ptl0) \
105 (write_cr3((uintptr_t) (ptl0)))
106#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
107 set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
108#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
109 set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
110#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
111 set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
112#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
113 set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
114
115/* Get PTE flags accessors for each level. */
116#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
117 get_pt_flags((pte_t *) (ptl0), (size_t) (i))
118#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
119 get_pt_flags((pte_t *) (ptl1), (size_t) (i))
120#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
121 get_pt_flags((pte_t *) (ptl2), (size_t) (i))
122#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
123 get_pt_flags((pte_t *) (ptl3), (size_t) (i))
124
125/* Set PTE flags accessors for each level. */
126#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
127 set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
128#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
129 set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
130#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
131 set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
132#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
133 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
134
135/* Set PTE present bit accessors for each level. */
136#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
137 set_pt_present((pte_t *) (ptl0), (size_t) (i))
138#define SET_PTL2_PRESENT_ARCH(ptl1, i) \
139 set_pt_present((pte_t *) (ptl1), (size_t) (i))
140#define SET_PTL3_PRESENT_ARCH(ptl2, i) \
141 set_pt_present((pte_t *) (ptl2), (size_t) (i))
142#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
143 set_pt_present((pte_t *) (ptl3), (size_t) (i))
144
145/* Macros for querying the last-level PTE entries. */
146#define PTE_VALID_ARCH(p) \
147 ((p)->soft_valid != 0)
148#define PTE_PRESENT_ARCH(p) \
149 ((p)->present != 0)
150#define PTE_GET_FRAME_ARCH(p) \
151 (((uintptr_t) (p)->addr_12_51) << 12)
152#define PTE_WRITABLE_ARCH(p) \
153 ((p)->writeable != 0)
154#define PTE_EXECUTABLE_ARCH(p) \
155 ((p)->no_execute == 0)
156
157#ifndef __ASSEMBLER__
158
159#include <arch/interrupt.h>
160#include <mm/mm.h>
161#include <trace.h>
162#include <typedefs.h>
163
164/* Page fault error codes. */
165
166/** When bit on this position is 0, the page fault was caused by a not-present
167 * page.
168 */
169#define PFERR_CODE_P (1 << 0)
170
171/** When bit on this position is 1, the page fault was caused by a write. */
172#define PFERR_CODE_RW (1 << 1)
173
174/** When bit on this position is 1, the page fault was caused in user mode. */
175#define PFERR_CODE_US (1 << 2)
176
177/** When bit on this position is 1, a reserved bit was set in page directory. */
178#define PFERR_CODE_RSVD (1 << 3)
179
180/** When bit on this position os 1, the page fault was caused during instruction
181 * fecth.
182 */
183#define PFERR_CODE_ID (1 << 4)
184
185/** Page Table Entry. */
186typedef struct {
187 unsigned int present : 1;
188 unsigned int writeable : 1;
189 unsigned int uaccessible : 1;
190 unsigned int page_write_through : 1;
191 unsigned int page_cache_disable : 1;
192 unsigned int accessed : 1;
193 unsigned int dirty : 1;
194 unsigned int unused : 1;
195 unsigned int global : 1;
196 unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
197 unsigned int avl : 2;
198 unsigned long addr_12_51 : 40;
199 unsigned int reserved : 11;
200 unsigned int no_execute : 1;
201} __attribute__((packed)) pte_t;
202
203_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
204{
205 pte_t *p = &pt[i];
206
207 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
208 (!p->present) << PAGE_PRESENT_SHIFT |
209 p->uaccessible << PAGE_USER_SHIFT |
210 1 << PAGE_READ_SHIFT |
211 p->writeable << PAGE_WRITE_SHIFT |
212 (!p->no_execute) << PAGE_EXEC_SHIFT |
213 p->global << PAGE_GLOBAL_SHIFT);
214}
215
216_NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
217{
218 pte_t *p = &pt[i];
219
220 p->addr_12_51 = (a >> 12) & UINT64_C(0xffffffffff);
221}
222
223_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
224{
225 pte_t *p = &pt[i];
226
227 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
228 p->present = !(flags & PAGE_NOT_PRESENT);
229 p->uaccessible = (flags & PAGE_USER) != 0;
230 p->writeable = (flags & PAGE_WRITE) != 0;
231 p->no_execute = (flags & PAGE_EXEC) == 0;
232 p->global = (flags & PAGE_GLOBAL) != 0;
233
234 /*
235 * Ensure that there is at least one bit set even if the present bit is cleared.
236 */
237 p->soft_valid = 1;
238}
239
240_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
241{
242 pte_t *p = &pt[i];
243
244 p->present = 1;
245}
246
247extern void page_arch_init(void);
248extern void page_fault(unsigned int, istate_t *);
249
250#endif /* __ASSEMBLER__ */
251
252#endif
253
254/** @}
255 */
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