| 1 | /*
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| 2 | * Copyright (c) 2005 Ondrej Palkovsky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup kernel_amd64_mm
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #ifndef KERN_amd64_PAGE_H_
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| 36 | #define KERN_amd64_PAGE_H_
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| 37 |
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| 38 | #include <arch/mm/frame.h>
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| 39 |
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| 40 | #define PAGE_WIDTH FRAME_WIDTH
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| 41 | #define PAGE_SIZE FRAME_SIZE
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| 42 |
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| 43 | #ifdef MEMORY_MODEL_kernel
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| 44 |
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| 45 | #ifndef __ASSEMBLER__
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| 46 |
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| 47 | #define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffffffff80000000))
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| 48 | #define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffffffff80000000))
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| 49 |
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| 50 | #else /* __ASSEMBLER__ */
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| 51 |
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| 52 | #define KA2PA(x) ((x) - 0xffffffff80000000)
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| 53 | #define PA2KA(x) ((x) + 0xffffffff80000000)
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| 54 |
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| 55 | #endif /* __ASSEMBLER__ */
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| 56 |
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| 57 | #endif /* MEMORY_MODEL_kernel */
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| 58 |
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| 59 | #ifdef MEMORY_MODEL_large
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| 60 |
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| 61 | #ifndef __ASSEMBLER__
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| 62 |
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| 63 | #define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
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| 64 | #define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
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| 65 |
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| 66 | #else /* __ASSEMBLER__ */
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| 67 |
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| 68 | #define KA2PA(x) ((x) - 0xffff800000000000)
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| 69 | #define PA2KA(x) ((x) + 0xffff800000000000)
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| 70 |
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| 71 | #endif /* __ASSEMBLER__ */
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| 72 |
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| 73 | #endif /* MEMORY_MODEL_large */
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| 74 |
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| 75 | /* Number of entries in each level. */
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| 76 | #define PTL0_ENTRIES_ARCH 512
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| 77 | #define PTL1_ENTRIES_ARCH 512
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| 78 | #define PTL2_ENTRIES_ARCH 512
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| 79 | #define PTL3_ENTRIES_ARCH 512
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| 80 |
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| 81 | /* Page table sizes for each level. */
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| 82 | #define PTL0_FRAMES_ARCH 1
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| 83 | #define PTL1_FRAMES_ARCH 1
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| 84 | #define PTL2_FRAMES_ARCH 1
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| 85 | #define PTL3_FRAMES_ARCH 1
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| 86 |
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| 87 | /* Macros calculating indices into page tables in each level. */
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| 88 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ffU)
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| 89 | #define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ffU)
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| 90 | #define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ffU)
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| 91 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ffU)
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| 92 |
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| 93 | /* Get PTE address accessors for each level. */
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| 94 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 95 | ((pte_t *) (((uint64_t) ((pte_t *) (ptl0))[(i)].addr_12_51) << 12))
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| 96 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 97 | ((pte_t *) (((uint64_t) ((pte_t *) (ptl1))[(i)].addr_12_51) << 12))
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| 98 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 99 | ((pte_t *) (((uint64_t) ((pte_t *) (ptl2))[(i)].addr_12_51) << 12))
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| 100 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 101 | ((uintptr_t *) (((uint64_t) ((pte_t *) (ptl3))[(i)].addr_12_51) << 12))
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| 102 |
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| 103 | /* Set PTE address accessors for each level. */
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| 104 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \
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| 105 | (write_cr3((uintptr_t) (ptl0)))
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| 106 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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| 107 | set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
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| 108 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
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| 109 | set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
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| 110 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
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| 111 | set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
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| 112 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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| 113 | set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
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| 114 |
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| 115 | /* Get PTE flags accessors for each level. */
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| 116 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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| 117 | get_pt_flags((pte_t *) (ptl0), (size_t) (i))
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| 118 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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| 119 | get_pt_flags((pte_t *) (ptl1), (size_t) (i))
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| 120 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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| 121 | get_pt_flags((pte_t *) (ptl2), (size_t) (i))
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| 122 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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| 123 | get_pt_flags((pte_t *) (ptl3), (size_t) (i))
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| 124 |
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| 125 | /* Set PTE flags accessors for each level. */
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| 126 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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| 127 | set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
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| 128 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
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| 129 | set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
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| 130 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
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| 131 | set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
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| 132 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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| 133 | set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
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| 134 |
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| 135 | /* Set PTE present bit accessors for each level. */
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| 136 | #define SET_PTL1_PRESENT_ARCH(ptl0, i) \
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| 137 | set_pt_present((pte_t *) (ptl0), (size_t) (i))
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| 138 | #define SET_PTL2_PRESENT_ARCH(ptl1, i) \
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| 139 | set_pt_present((pte_t *) (ptl1), (size_t) (i))
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| 140 | #define SET_PTL3_PRESENT_ARCH(ptl2, i) \
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| 141 | set_pt_present((pte_t *) (ptl2), (size_t) (i))
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| 142 | #define SET_FRAME_PRESENT_ARCH(ptl3, i) \
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| 143 | set_pt_present((pte_t *) (ptl3), (size_t) (i))
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| 144 |
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| 145 | /* Macros for querying the last-level PTE entries. */
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| 146 | #define PTE_VALID_ARCH(p) \
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| 147 | ((p)->soft_valid != 0)
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| 148 | #define PTE_PRESENT_ARCH(p) \
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| 149 | ((p)->present != 0)
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| 150 | #define PTE_GET_FRAME_ARCH(p) \
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| 151 | (((uintptr_t) (p)->addr_12_51) << 12)
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| 152 | #define PTE_WRITABLE_ARCH(p) \
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| 153 | ((p)->writeable != 0)
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| 154 | #define PTE_EXECUTABLE_ARCH(p) \
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| 155 | ((p)->no_execute == 0)
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| 156 |
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| 157 | #ifndef __ASSEMBLER__
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| 158 |
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| 159 | #include <arch/interrupt.h>
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| 160 | #include <mm/mm.h>
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| 161 | #include <trace.h>
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| 162 | #include <typedefs.h>
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| 163 |
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| 164 | /* Page fault error codes. */
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| 165 |
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| 166 | /** When bit on this position is 0, the page fault was caused by a not-present
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| 167 | * page.
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| 168 | */
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| 169 | #define PFERR_CODE_P (1 << 0)
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| 170 |
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| 171 | /** When bit on this position is 1, the page fault was caused by a write. */
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| 172 | #define PFERR_CODE_RW (1 << 1)
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| 173 |
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| 174 | /** When bit on this position is 1, the page fault was caused in user mode. */
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| 175 | #define PFERR_CODE_US (1 << 2)
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| 176 |
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| 177 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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| 178 | #define PFERR_CODE_RSVD (1 << 3)
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| 179 |
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| 180 | /** When bit on this position os 1, the page fault was caused during instruction
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| 181 | * fecth.
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| 182 | */
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| 183 | #define PFERR_CODE_ID (1 << 4)
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| 184 |
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| 185 | /** Page Table Entry. */
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| 186 | typedef struct {
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| 187 | unsigned int present : 1;
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| 188 | unsigned int writeable : 1;
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| 189 | unsigned int uaccessible : 1;
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| 190 | unsigned int page_write_through : 1;
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| 191 | unsigned int page_cache_disable : 1;
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| 192 | unsigned int accessed : 1;
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| 193 | unsigned int dirty : 1;
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| 194 | unsigned int unused : 1;
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| 195 | unsigned int global : 1;
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| 196 | unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */
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| 197 | unsigned int avl : 2;
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| 198 | unsigned long addr_12_51 : 40;
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| 199 | unsigned int reserved : 11;
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| 200 | unsigned int no_execute : 1;
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| 201 | } __attribute__((packed)) pte_t;
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| 202 |
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| 203 | _NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
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| 204 | {
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| 205 | pte_t *p = &pt[i];
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| 206 |
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| 207 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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| 208 | (!p->present) << PAGE_PRESENT_SHIFT |
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| 209 | p->uaccessible << PAGE_USER_SHIFT |
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| 210 | 1 << PAGE_READ_SHIFT |
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| 211 | p->writeable << PAGE_WRITE_SHIFT |
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| 212 | (!p->no_execute) << PAGE_EXEC_SHIFT |
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| 213 | p->global << PAGE_GLOBAL_SHIFT);
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| 214 | }
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| 215 |
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| 216 | _NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
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| 217 | {
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| 218 | pte_t *p = &pt[i];
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| 219 |
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| 220 | p->addr_12_51 = (a >> 12) & UINT64_C(0xffffffffff);
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| 221 | }
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| 222 |
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| 223 | _NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
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| 224 | {
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| 225 | pte_t *p = &pt[i];
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| 226 |
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| 227 | p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 228 | p->present = !(flags & PAGE_NOT_PRESENT);
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| 229 | p->uaccessible = (flags & PAGE_USER) != 0;
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| 230 | p->writeable = (flags & PAGE_WRITE) != 0;
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| 231 | p->no_execute = (flags & PAGE_EXEC) == 0;
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| 232 | p->global = (flags & PAGE_GLOBAL) != 0;
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| 233 |
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| 234 | /*
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| 235 | * Ensure that there is at least one bit set even if the present bit is cleared.
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| 236 | */
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| 237 | p->soft_valid = 1;
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| 238 | }
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| 239 |
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| 240 | _NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
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| 241 | {
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| 242 | pte_t *p = &pt[i];
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| 243 |
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| 244 | p->present = 1;
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| 245 | }
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| 246 |
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| 247 | extern void page_arch_init(void);
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| 248 | extern void page_fault(unsigned int, istate_t *);
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| 249 |
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| 250 | #endif /* __ASSEMBLER__ */
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| 251 |
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| 252 | #endif
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| 253 |
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| 254 | /** @}
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| 255 | */
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