Changeset dd0c8a0 in mainline for kernel/genarch/include


Ignore:
Timestamp:
2013-09-29T06:56:33Z (12 years ago)
Author:
Beniamino Galvani <b.galvani@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a9bd960d
Parents:
3deb0155 (diff), 13be2583 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/genarch/include/genarch
Files:
3 added
2 deleted
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/genarch/include/genarch/drivers/am335x/irc.h

    r3deb0155 rdd0c8a0  
    3838#define KERN_AM335x_IRQC_H_
    3939
    40 #define AM335x_IRC_BASE_ADDRESS 0x48200000
    41 #define AM335x_IRC_SIZE         4096
     40#define AM335x_IRC_BASE_ADDRESS     0x48200000
     41#define AM335x_IRC_SIZE             4096
    4242
    43 #define AM335x_IRC_IRQ_COUNT    128
     43#define AM335x_IRC_IRQ_COUNT        128
     44#define AM335x_IRC_IRQ_GROUPS_COUNT 4
    4445
    45 #include <typedefs.h>
     46#define OMAP_IRC_IRQ_COUNT        AM335x_IRC_IRQ_COUNT
     47#define OMAP_IRC_IRQ_GROUPS_COUNT AM335x_IRC_IRQ_GROUPS_COUNT
    4648
    47 typedef struct {
    48         const ioport32_t revision;
    49 #define AM335x_IRC_REV_MASK 0xFF
    50 
    51         const uint8_t padd0[12];
    52 
    53         /* This register controls the various parameters
    54          * of the OCP interface.
    55          */
    56         ioport32_t sysconfig;
    57 #define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG   (1 << 0)
    58 #define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
    59 
    60         /* This register provides status information about the module */
    61         const ioport32_t sysstatus;
    62 #define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
    63 
    64         const uint8_t padd1[40];
    65 
    66         /* This register supplies the currently active IRQ interrupt number */
    67         ioport32_t sir_irq;
    68 #define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK       0x7F
    69 #define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
    70 
    71         /* This register supplies the currently active FIQ interrupt number */
    72         const ioport32_t sir_fiq;
    73 #define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK       0x7F
    74 #define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8
    75 
    76         /* This register contains the new interrupt agreement bits */
    77         ioport32_t control;
    78 #define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG       (1 << 0)
    79 #define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG       (1 << 1)
    80 
    81         /* This register controls protection of the other registers.
    82          * This register can only be accessed in priviledged mode, regardless
    83          * of the current value of the protection bit.
    84          */
    85         ioport32_t protection;
    86 #define AM335x_IRC_PROTECTION_FLAG              (1 << 0)
    87 
    88         /* This register controls the clock auto-idle for the functional
    89          * clock and the input synchronizers.
    90          */
    91         ioport32_t idle;
    92 #define AM335x_IRC_IDLE_FUNCIDLE_FLAG           (1 << 0)
    93 #define AM335x_IRC_IDLE_TURBO_FLAG              (1 << 1)
    94 
    95         const uint8_t padd2[12];
    96 
    97         /* This register supplies the currently active IRQ priority level */
    98         const ioport32_t irq_priority;
    99 #define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK     0x7F
    100 #define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
    101 
    102         /* This register supplies the currently active FIQ priority level */
    103         const ioport32_t fiq_priority;
    104 #define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK     0x7F
    105 #define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
    106 
    107         /* This register sets the priority threshold */
    108         ioport32_t threshold;
    109 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK     0xFF
    110 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED  0x00
    111 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF
    112 
    113         const uint8_t padd[20];
    114 
    115         struct {
    116                 /* Raw interrupt input status before masking */
    117                 const ioport32_t itr;
    118 
    119                 /* Interrupt mask */
    120                 ioport32_t mir;
    121 
    122                 /* This register is used to clear the interrupt mask bits,
    123                  * Write 1 clears the mask bit to 0.
    124                  */
    125                 ioport32_t mir_clear;
    126 
    127                 /* This register is used to set the interrupt mask bits,
    128                  * Write 1 sets the mask bit to 1.
    129                  */
    130                 ioport32_t mir_set;
    131 
    132                 /* This register is used to set the software interrupt bits,
    133                  * it is also used to read the current active software
    134                  * interrupts.
    135                  * Write 1 sets the software interrups bits to 1.
    136                  */
    137                 ioport32_t isr_set;
    138 
    139                 /* This register is used to clear the software interrups bits.
    140                  * Write 1 clears the software interrupt bits to 0.
    141                  */
    142                 ioport32_t isr_clear;
    143 
    144                 /* This register contains the IRQ status after masking. */
    145                 const ioport32_t pending_irq;
    146 
    147                 /* This register contains the FIQ status after masking. */
    148                 const ioport32_t pending_fiq;
    149         } interrupts[4];
    150 
    151         /* These registers contain the priority for the interrups and
    152          * the FIQ/IRQ steering.
    153          */
    154         ioport32_t ilr[AM335x_IRC_IRQ_COUNT];
    155 /* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */
    156 #define AM335x_IRC_ILR_FIQNIRQ_FLAG    (1 << 0)
    157 #define AM335x_IRC_ILR_PRIORITY_MASK   0x3F
    158 #define AM335x_IRC_ILR_PRIORITY_SHIFT  2
    159 
    160 } am335x_irc_regs_t;
    161 
    162 static inline void am335x_irc_init(am335x_irc_regs_t *regs)
    163 {
    164         int i;
    165 
    166         /* Initialization sequence */
    167 
    168         /* 1 - Program the SYSCONFIG register: if necessary, enable the
    169          *     autogating by setting the AUTOIDLE bit.
    170          */
    171         regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
    172 
    173         /* 2 - Program the IDLE register: if necessary, disable functional
    174          *     clock autogating or enable synchronizer autogating by setting
    175          *     the FUNCIDLE bit or the TURBO bit accordingly.
    176          */
    177         regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG;
    178         regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG;
    179 
    180         /* 3 - Program ILRm register for each interrupt line: Assign a
    181          *     priority level and set the FIQNIRQ bit for an FIQ interrupt
    182          *     (by default, interrupts are mapped to IRQ and
    183          *     priority is 0 (highest).
    184          */
    185 
    186         for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i)
    187                 regs->ilr[i] = 0;
    188 
    189         /* 4 - Program the MIRn register: Enable interrupts (by default,
    190          *     all interrupt lines are masked).
    191          */
    192         for (i = 0; i < 4; ++i)
    193                 regs->interrupts[i].mir_set = 0xFFFFFFFF;
    194 }
    195 
    196 /** Get the currently active IRQ interrupt number
    197  *
    198  * @param regs     Pointer to the irc memory mapped registers
    199  *
    200  * @return         The active IRQ interrupt number
    201  */
    202 static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs)
    203 {
    204         return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
    205 }
    206 
    207 /** Reset IRQ output and enable new IRQ generation
    208  *
    209  * @param regs    Pointer to the irc memory mapped registers
    210  */
    211 static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs)
    212 {
    213         regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG;
    214 }
    215 
    216 /** Reset FIQ output and enable new FIQ generation
    217  *
    218  * @param regs    Pointer to the irc memory mapped registers
    219  */
    220 static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs)
    221 {
    222         regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG;
    223 }
    224 
    225 /** Clear an interrupt mask bit
    226  *
    227  * @param regs    Pointer to the irc memory mapped registers
    228  * @param inum    The interrupt to be enabled
    229  */
    230 static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum)
    231 {
    232         ASSERT(inum < AM335x_IRC_IRQ_COUNT);
    233         const unsigned set = inum / 32;
    234         const unsigned pos = inum % 32;
    235         regs->interrupts[set].mir_clear = (1 << pos);
    236 }
    237 
    238 /** Set an interrupt mask bit
    239  *
    240  * @param regs    Pointer to the irc memory mapped registers
    241  * @param inum    The interrupt to be disabled
    242  */
    243 static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum)
    244 {
    245         ASSERT(inum < AM335x_IRC_IRQ_COUNT);
    246         const unsigned set = inum / 32;
    247         const unsigned pos = inum % 32;
    248         regs->interrupts[set].mir_set = (1 << pos);
    249 }
     49#include <genarch/drivers/omap/irc.h>
    25050
    25151#endif

  • kernel/genarch/include/genarch/drivers/am335x/uart.h

    r3deb0155 rdd0c8a0  
    3737#define _KERN_AM335X_UART_H_
    3838
    39 #include "uart_regs.h"
     39#include <genarch/drivers/omap/uart.h>
    4040
    4141#define AM335x_UART0_BASE_ADDRESS    0x44E09000
    … …  
    6363#define AM335x_UART5_IRQ             46
    6464
    65 typedef struct {
    66         am335x_uart_regs_t *regs;
    67         indev_t *indev;
    68         outdev_t outdev;
    69         irq_t irq;
    70 } am335x_uart_t;
    71 
    72 #ifdef CONFIG_AM335X_UART
    73 extern bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt,
    74     uintptr_t addr, size_t size);
    75 
    76 extern void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev);
    77 #else
    78 static bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt,
    79     uintptr_t addr, size_t size)
    80 { return true; }
    81 
    82 static void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev) {}
    83 #endif
    84 
    8565#endif
    8666

  • kernel/genarch/include/genarch/drivers/amdm37x/gpt.h

    r3deb0155 rdd0c8a0  
    3939#include <typedefs.h>
    4040#include <mm/km.h>
     41#include <time/clock.h>
    4142
    4243/* AMDM37x TRM p. 2740 */
    … …  
    128129#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
    129130#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
    130 #define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
    131 #define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
    132 #define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
    133 #define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
     131#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3 << 8)
     132#define AMDM37x_GPT_TCLR_TCM_NO_CAPTURE   (0x0 << 8)
     133#define AMDM37x_GPT_TCLR_TCM_RAISE_CAPTURE   (0x1 << 8)
     134#define AMDM37x_GPT_TCLR_TCM_FALL_CAPTURE   (0x2 << 8)
     135#define AMDM37x_GPT_TCLR_TCM_BOTH_CAPTURE   (0x3 << 8)
     136#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3 << 10)
     137#define AMDM37x_GPT_TCLR_TRG_NO  (0x0 << 10)
     138#define AMDM37x_GPT_TCLR_TRG_OVERFLOW  (0x1 << 10)
     139#define AMDM37x_GPT_TCLR_TRG_OVERMATCH  (0x2 << 10)
    134140#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
    135141#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
    … …  
    209215        timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
    210216
     217        /* Reset the timer */
     218        timer->regs->tiocp_cfg |= AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG;
     219
     220        while (!(timer->regs->tistat & AMDM37x_GPT_TISTAT_RESET_DONE_FLAG));
     221
    211222        /* Set autoreload */
    212         timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
     223        timer->regs->tclr |= AMDM37x_GPT_TCLR_AR_FLAG;
    213224
    214225        timer->special_available = (
    … …  
    216227            (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
    217228            (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
     229        /* Select reload value */
    218230        timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
     231        /* Set current counter value */
    219232        timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
     233
    220234        if (timer->special_available) {
    221                 /* Set values for according to formula (manual p. 2733) */
     235                /* Set values according to formula (manual p. 2733) */
    222236                /* Use temporary variables for easier debugging */
    223237                const uint32_t tpir =
    224238                    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
    225239                const uint32_t tnir =
    226                     ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
     240                    ((32768 / hz) * 1000000) - (32768000L * (1000 / hz));
    227241                timer->regs->tpir = tpir;
    228242                timer->regs->tnir = tnir;
    … …  
    241255}
    242256
    243 static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
     257static inline bool amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
    244258{
    245259        ASSERT(timer);
    246260        ASSERT(timer->regs);
    247261        /* Clear all pending interrupts */
    248         timer->regs->tisr = timer->regs->tisr;
     262        const uint32_t tisr = timer->regs->tisr;
     263        timer->regs->tisr = tisr;
     264        return tisr != 0;
    249265}
    250266

  • kernel/genarch/include/genarch/drivers/amdm37x/irc.h

    r3deb0155 rdd0c8a0  
    3838
    3939/* AMDM37x TRM p. 1079 */
    40 #define AMDM37x_IRC_BASE_ADDRESS 0x48200000
    41 #define AMDM37x_IRC_SIZE 4096
     40#define AMDM37x_IRC_BASE_ADDRESS     0x48200000
     41#define AMDM37x_IRC_SIZE             4096
    4242
    43 #define AMDM37x_IRC_IRQ_COUNT 96
     43#define AMDM37x_IRC_IRQ_COUNT        96
     44#define AMDM37x_IRC_IRQ_GROUPS_COUNT 3
    4445
    45 #include <typedefs.h>
     46#define OMAP_IRC_IRQ_COUNT        AMDM37x_IRC_IRQ_COUNT
     47#define OMAP_IRC_IRQ_GROUPS_COUNT AMDM37x_IRC_IRQ_GROUPS_COUNT
    4648
    47 typedef struct {
    48         const ioport32_t revision; /**< Revision */
    49 #define AMDM37x_IRC_REV_MASK (0xff)
    50 
    51         uint8_t padd0_[12];
    52 
    53         ioport32_t sysconfig; /**< SYS config */
    54 #define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
    55 #define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
    56 
    57         const ioport32_t sysstatus; /**< SYS status */
    58 #define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
    59 
    60         uint8_t padd1_[40];
    61 
    62         const ioport32_t sir_irq;   /**< Currently active irq number */
    63 #define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
    64 #define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
    65 
    66         const ioport32_t sir_fiq;
    67 #define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
    68 #define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
    69 
    70         ioport32_t control;   /**< New interrupt agreement. */
    71 #define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
    72 #define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
    73 
    74         ioport32_t protection;  /**< Protect other registers. */
    75 #define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
    76 
    77         ioport32_t idle;   /**< Idle and autogating */
    78 #define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
    79 #define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
    80 
    81         uint8_t padd2_[12];
    82 
    83         ioport32_t irq_priority; /**< Active IRQ priority */
    84 #define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
    85 #define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
    86 
    87         ioport32_t fiq_priority; /**< Active FIQ priority */
    88 #define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
    89 #define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
    90 
    91         ioport32_t threshold; /**< Priority threshold */
    92 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
    93 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
    94 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
    95 
    96         uint8_t padd3__[20];
    97 
    98         struct {
    99                 const ioport32_t itr;   /**< Interrupt input status before masking */
    100                 ioport32_t mir;   /**< Interrupt mask */
    101                 ioport32_t mir_clear; /**< Clear mir mask bits */
    102                 ioport32_t mir_set;   /**< Set mir mask bits */
    103                 ioport32_t isr_set;   /**< Set software interrupt bits */
    104                 ioport32_t isr_clear; /**< Clear software interrupt bits */
    105                 const ioport32_t pending_irq; /**< IRQ status after masking */
    106                 const ioport32_t pending_fiq; /**< FIQ status after masking */
    107         } interrupts[3];
    108 
    109         uint8_t padd4_[32];
    110 
    111         ioport32_t ilr[96];   /**< FIQ/IRQ steering */
    112 #define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
    113 #define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
    114 #define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
    115 
    116 } amdm37x_irc_regs_t;
    117 
    118 static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
    119 {
    120 #define DUMP_REG(name) \
    121         printf("%s %p(%x).\n", #name, &regs->name, regs->name);
    122 
    123         DUMP_REG(revision);
    124         DUMP_REG(sysconfig);
    125         DUMP_REG(sysstatus);
    126         DUMP_REG(sir_irq);
    127         DUMP_REG(sir_fiq);
    128         DUMP_REG(control);
    129         DUMP_REG(protection);
    130         DUMP_REG(idle);
    131         DUMP_REG(irq_priority);
    132         DUMP_REG(fiq_priority);
    133         DUMP_REG(threshold);
    134 
    135         for (int i = 0; i < 3; ++i) {
    136                 DUMP_REG(interrupts[i].itr);
    137                 DUMP_REG(interrupts[i].mir);
    138                 DUMP_REG(interrupts[i].isr_set);
    139                 DUMP_REG(interrupts[i].pending_irq);
    140                 DUMP_REG(interrupts[i].pending_fiq);
    141         }
    142         for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
    143                 DUMP_REG(ilr[i]);
    144         }
    145 
    146 #undef DUMP_REG
    147 }
    148 
    149 static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
    150 {
    151         /* AMDM37x TRM sec 12.5.1 p. 2425 */
    152         /* Program system config register */
    153         //TODO enable this when you know the meaning
    154         //regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
    155 
    156         /* Program idle register */
    157         //TODO enable this when you know the meaning
    158         //regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
    159 
    160         /* Program ilr[m] assign priority, decide fiq */
    161         for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
    162                 regs->ilr[i] = 0; /* highest prio(default) route to irq */
    163         }
    164 
    165         /* Disable all interrupts */
    166         regs->interrupts[0].mir_set = 0xffffffff;
    167         regs->interrupts[1].mir_set = 0xffffffff;
    168         regs->interrupts[2].mir_set = 0xffffffff;
    169 }
    170 
    171 static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
    172 {
    173         return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
    174 }
    175 
    176 static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
    177 {
    178         regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
    179 }
    180 
    181 static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
    182 {
    183         regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
    184 }
    185 
    186 static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
    187 {
    188         ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
    189         const unsigned set = inum / 32;
    190         const unsigned pos = inum % 32;
    191         regs->interrupts[set].mir_clear = (1 << pos);
    192 }
    193 
    194 static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
    195 {
    196         ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
    197         const unsigned set = inum / 32;
    198         const unsigned pos = inum % 32;
    199         regs->interrupts[set].mir_set = (1 << pos);
    200 }
     49#include <genarch/drivers/omap/irc.h>
    20150
    20251#endif

  • kernel/genarch/include/genarch/drivers/amdm37x/uart.h

    r3deb0155 rdd0c8a0  
    3737#define _AMDM37x_UART_H_
    3838
    39 #include "uart_regs.h"
     39#include <genarch/drivers/omap/uart.h>
    4040
    4141/* AMDM37x TRM p. 2950 */
    … …  
    5656#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
    5757
    58 typedef struct {
    59         amdm37x_uart_regs_t *regs;
    60         indev_t *indev;
    61         outdev_t outdev;
    62         irq_t irq;
    63 } amdm37x_uart_t;
    64 
    65 
    66 bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
    67 void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
    68 
    6958#endif
    7059

  • kernel/genarch/include/genarch/mm/page_pt.h

    r3deb0155 rdd0c8a0  
    5858#define PTL3_ENTRIES  PTL3_ENTRIES_ARCH
    5959
    60 /* Table sizes in each level */
    61 #define PTL0_SIZE  PTL0_SIZE_ARCH
    62 #define PTL1_SIZE  PTL1_SIZE_ARCH
    63 #define PTL2_SIZE  PTL2_SIZE_ARCH
    64 #define PTL3_SIZE  PTL3_SIZE_ARCH
     60/* Table sizes in each level (in frames) */
     61#define PTL0_FRAMES  PTL0_FRAMES_ARCH
     62#define PTL1_FRAMES  PTL1_FRAMES_ARCH
     63#define PTL2_FRAMES  PTL2_FRAMES_ARCH
     64#define PTL3_FRAMES  PTL3_FRAMES_ARCH
     65
     66/* Table sizes in each level (in bytes) */
     67#define PTL0_SIZE  FRAMES2SIZE(PTL0_FRAMES)
     68#define PTL1_SIZE  FRAMES2SIZE(PTL1_FRAMES)
     69#define PTL2_SIZE  FRAMES2SIZE(PTL2_FRAMES)
     70#define PTL3_SIZE  FRAMES2SIZE(PTL3_FRAMES)
    6571
    6672/*
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