Changeset dd0c8a0 in mainline for kernel/arch/arm32/include


Ignore:
Timestamp:
2013-09-29T06:56:33Z (12 years ago)
Author:
Beniamino Galvani <b.galvani@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a9bd960d
Parents:
3deb0155 (diff), 13be2583 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/arm32/include/arch
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/arch/asm.h

    r3deb0155 rdd0c8a0  
    3838
    3939#include <typedefs.h>
     40#include <arch/cp15.h>
    4041#include <arch/stack.h>
    4142#include <config.h>
    … …  
    5152 * chapter 2.3.8 p.2-22 (52 in the PDF)
    5253 *
    53  * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
    54  * reference manual for armv4/5 CP15 implementation is mandatory only for
    55  * armv6+.
     54 * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM
     55 * Architecture reference manual for armv4/5, CP15 implementation is mandatory
     56 * only for armv6+.
    5657 */
    5758NO_TRACE static inline void cpu_sleep(void)
    … …  
    6061        asm volatile ( "wfe" );
    6162#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
    62         asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
     63        WFI_write(0);
    6364#endif
    6465}

  • kernel/arch/arm32/include/arch/cp15.h

    r3deb0155 rdd0c8a0  
    171171        CCSIDR_LINESIZE_MASK = 0x7,
    172172        CCSIDR_LINESIZE_SHIFT = 0,
     173#define CCSIDR_SETS(val) \
     174        (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
     175#define CCSIDR_WAYS(val) \
     176        (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
     177/* The register value is log(linesize_in_words) - 2 */
     178#define CCSIDR_LINESIZE_LOG(val) \
     179        (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
    173180};
    174181CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
    … …  
    187194        CLIDR_UNI_CACHE = 0x4,
    188195        CLIDR_CACHE_MASK = 0x7,
    189 #define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
     196/** levels counted from 0 */
     197#define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
    190198};
    191199CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
    … …  
    294302
    295303/* Memory protection and control registers */
     304enum {
     305        TTBR_ADDR_MASK = 0xffffff80,
     306        TTBR_NOS_FLAG = 1 << 5,
     307        TTBR_RGN_MASK = 0x3 << 3,
     308        TTBR_RGN_NO_CACHE = 0x0 << 3,
     309        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
     310        TTBR_RGN_WT_CACHE = 0x2 << 3,
     311        TTBR_RGN_WB_CACHE = 0x3 << 3,
     312        TTBR_S_FLAG = 1 << 1,
     313        TTBR_C_FLAG = 1 << 0,
     314};
    296315CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
    297316CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
    … …  
    364383
    365384CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
    366 CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2);
     385CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
    367386
    368387CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
    … …  
    370389CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
    371390CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
    372 CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4);
    373 CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5);
    374 CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6);
    375 CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7);
     391CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
     392CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
     393CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
     394CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
    376395
    377396

  • kernel/arch/arm32/include/arch/mm/frame.h

    r3deb0155 rdd0c8a0  
    3939#define FRAME_WIDTH  12  /* 4KB frames */
    4040#define FRAME_SIZE   (1 << FRAME_WIDTH)
     41
     42#define FRAME_LOWPRIO  0
    4143
    4244#ifndef __ASM__

  • kernel/arch/arm32/include/arch/mm/page.h

    r3deb0155 rdd0c8a0  
    4141#include <arch/exception.h>
    4242#include <arch/barrier.h>
     43#include <arch/cp15.h>
    4344#include <trace.h>
    4445
    … …  
    7273
    7374/* Page table sizes for each level. */
    74 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    75 #define PTL1_SIZE_ARCH          0
    76 #define PTL2_SIZE_ARCH          0
    77 #define PTL3_SIZE_ARCH          ONE_FRAME
     75#define PTL0_FRAMES_ARCH  4
     76#define PTL1_FRAMES_ARCH  1
     77#define PTL2_FRAMES_ARCH  1
     78#define PTL3_FRAMES_ARCH  1
    7879
    7980/* Macros calculating indices into page tables for each level. */
    … …  
    9596/* Set PTE address accessors for each level. */
    9697#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    97         (set_ptl0_addr((pte_t *) (ptl0)))
     98        set_ptl0_addr((pte_t *) (ptl0))
    9899#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    99         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
     100        set_ptl1_addr((pte_t*) (ptl0), i, a)
    100101#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    101102#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    102103#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    103         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
     104        set_ptl3_addr((pte_t*) (ptl3), i, a)
    104105
    105106/* Get PTE flags accessors for each level. */
    … …  
    129130        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    130131
     132
     133#define pt_coherence(page) pt_coherence_m(page, 1)
     134
    131135#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
    132136#include "page_armv6.h"
    … …  
    137141#endif
    138142
     143/** Sets the address of level 0 page table.
     144 *
     145 * @param pt Pointer to the page table to set.
     146 *
     147 * Page tables are always in cacheable memory.
     148 * Make sure the memory type is correct, and in sync with:
     149 * init_boot_pt (boot/arch/arm32/src/mm.c)
     150 * init_ptl0_section (boot/arch/arm32/src/mm.c)
     151 * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     152 */
     153NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
     154{
     155        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
     156        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
     157        TTBR0_write(val);
     158}
     159
     160NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
     161{
     162        pt[i].l0.coarse_table_addr = address >> 10;
     163        pt_coherence(&pt[i].l0);
     164}
     165
     166NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
     167{
     168        pt[i].l1.frame_base_addr = address >> 12;
     169        pt_coherence(&pt[i].l1);
     170}
     171
    139172#endif
    140173

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    r3deb0155 rdd0c8a0  
    120120#define PTE_DESCRIPTOR_SMALL_PAGE       2
    121121
    122 
    123 /** Sets the address of level 0 page table.
    124  *
    125  * @param pt Pointer to the page table to set.
    126  *
    127  */
    128 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    129 {
    130         asm volatile (
    131                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    132                 :: [pt] "r" (pt)
    133         );
    134 }
    135 
     122#define pt_coherence_m(pt, count) \
     123do { \
     124        for (unsigned i = 0; i < count; ++i) \
     125                DCCMVAU_write((uintptr_t)(pt + i)); \
     126        read_barrier(); \
     127} while (0)
    136128
    137129/** Returns level 0 page table entry flags.
    … …  
    223215       
    224216        /* default access permission */
    225         p->access_permission_0 = p->access_permission_1 = 
     217        p->access_permission_0 = p->access_permission_1 =
    226218            p->access_permission_2 = p->access_permission_3 =
    227219            PTE_AP_USER_NO_KERNEL_RW;
    … …  
    229221        if (flags & PAGE_USER)  {
    230222                if (flags & PAGE_READ) {
    231                         p->access_permission_0 = p->access_permission_1 = 
    232                             p->access_permission_2 = p->access_permission_3 = 
     223                        p->access_permission_0 = p->access_permission_1 =
     224                            p->access_permission_2 = p->access_permission_3 =
    233225                            PTE_AP_USER_RO_KERNEL_RW;
    234226                }
    235227                if (flags & PAGE_WRITE) {
    236                         p->access_permission_0 = p->access_permission_1 = 
    237                             p->access_permission_2 = p->access_permission_3 = 
    238                             PTE_AP_USER_RW_KERNEL_RW; 
     228                        p->access_permission_0 = p->access_permission_1 =
     229                            p->access_permission_2 = p->access_permission_3 =
     230                            PTE_AP_USER_RW_KERNEL_RW;
    239231                }
    240232        }

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    r3deb0155 rdd0c8a0  
    4040#error "Do not include arch specific page.h directly use generic page.h instead"
    4141#endif
     42
    4243
    4344/* Macros for querying the last-level PTE entries. */
    … …  
    125126#define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
    126127
    127 /** Sets the address of level 0 page table.
    128  *
    129  * @param pt Pointer to the page table to set.
    130  *
    131  */
    132 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    133 {
    134         asm volatile (
    135                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    136                 :: [pt] "r" (pt)
    137         );
    138 }
     128
     129/**
     130 * For an ARMv7 implementation that does not include the Large Physical Address Extension,
     131 * and in implementations of architecture versions before ARMv7, if the translation tables
     132 * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of
     133 * unification after writing to the translation tables and before the DSB instruction. This
     134 * ensures that the updated translation table are visible to a hardware translation table walk.
     135 *
     136 * Therefore, an example instruction sequence for writing a translation table entry,
     137 * covering changes to the instruction
     138 * or data mappings in a uniprocessor system is:
     139 * STR rx, [Translation table entry]
     140 * ; write new entry to the translation table
     141 * Clean cache line [Translation table entry] : This operation is not required with the
     142 * ; Multiprocessing Extensions.
     143 * DSB
     144 * ; ensures visibility of the data cleaned from the D Cache
     145 * Invalidate TLB entry by MVA (and ASID if non-global) [page address]
     146 * Invalidate BTC
     147 * DSB
     148 * ; ensure completion of the Invalidate TLB operation
     149 * ISB
     150 * ; ensure table changes visible to instruction fetch
     151 *
     152 * ARM Architecture reference chp. B3.10.1 p. B3-1375
     153 * @note: see TTRB0/1 for pt memory type
     154 */
     155#define pt_coherence_m(pt, count) \
     156do { \
     157        for (unsigned i = 0; i < count; ++i) \
     158                DCCMVAU_write((uintptr_t)(pt + i)); \
     159        read_barrier(); \
     160} while (0)
    139161
    140162
    … …  
    206228                p->ns = 0;
    207229        }
     230        pt_coherence(p);
    208231}
    209232
    … …  
    232255                        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX;
    233256        }
    234        
    235         /* tex=0 buf=1 and cache=1 => normal memory
    236          * tex=0 buf=1 and cache=0 => shareable device mmio
    237          */
    238         p->cacheable = (flags & PAGE_CACHEABLE);
    239         p->bufferable = 1;
    240         p->tex = 0;
     257
     258        if (flags & PAGE_CACHEABLE) {
     259                /*
     260                 * Write-through, no write-allocate memory, see ch. B3.8.2
     261                 * (p. B3-1358) of ARM Architecture reference manual.
     262                 * Make sure the memory type is correct, and in sync with:
     263                 * init_boot_pt (boot/arch/arm32/src/mm.c)
     264                 * init_ptl0_section (boot/arch/arm32/src/mm.c)
     265                 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     266                 */
     267                p->tex = 5;
     268                p->cacheable = 0;
     269                p->bufferable = 1;
     270        } else {
     271                /*
     272                 * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of
     273                 * ARM Architecture reference manual.
     274                 */
     275                p->tex = 0;
     276                p->cacheable = 0;
     277                p->bufferable = 1;
     278        }
    241279       
    242280        /* Shareable is ignored for devices (non-cacheable),
    243          * turn it on for normal memory. */
    244         p->shareable = 1;
     281         * turn it off for normal memory. */
     282        p->shareable = 0;
    245283       
    246284        p->non_global = !(flags & PAGE_GLOBAL);
    … …  
    256294                        p->access_permission_1 = PTE_AP1_RO;
    257295        }
     296        pt_coherence(p);
    258297}
    259298
    … …  
    264303        p->should_be_zero_0 = 0;
    265304        p->should_be_zero_1 = 0;
    266         write_barrier();
    267305        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
     306        pt_coherence(p);
    268307}
    269308
    … …  
    273312
    274313        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
     314        pt_coherence(p);
    275315}
    276316
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