Changeset dd0c8a0 in mainline for boot/arch/arm32/src

Timestamp:

2013-09-29T06:56:33Z (12 years ago)

Author:

Beniamino Galvani <b.galvani@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a9bd960d

Parents:

3deb0155 (diff), 13be2583 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

boot/arch/arm32/src

Files:

• asm.S (modified) (3 diffs)
• main.c (modified) (4 diffs)
• mm.c (modified) (6 diffs)

boot/arch/arm32/src/asm.S

@@ -56 +56 @@
 jump_to_kernel:
         #
-        # TODO
         # Make sure that the I-cache, D-cache and memory are mutually coherent
         # before passing control to the copied code.
@@ -68 +67 @@
 #define CP15_C1_BP              11
 #define CP15_C1_DC              2
-        # Disable I-cache and D-cache before the kernel is started.
+
+
+#ifndef PROCESSOR_ARCH_armv7_a
         mrc     p15, 0, r4, c1, c0, 0
+        
+        # D-cache before the kernel is started.
         bic     r4, r4, #(1 << CP15_C1_DC)
+
+        # Disable I-cache and Branche predictors.
         bic     r4, r4, #(1 << CP15_C1_IC)
         bic     r4, r4, #(1 << CP15_C1_BP)
+        
         mcr     p15, 0, r4, c1, c0, 0
+#endif
+
 
         
@@ -81 +89 @@
 #else
         #cp15 dsb, r4 is ignored (should be zero)
+        mov r4, #0
         mcr p15, 0, r4, c7, c10, 4
 #endif
         
         # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mov r4, #0
         mcr p15, 0, r4, c7, c5, 0
         nop

boot/arch/arm32/src/main.c

@@ -53 +53 @@
 extern void *bdata_end;
 
-
-static inline void invalidate_icache(void)
-{
-        /* ICIALLU Invalidate entire ICache */
-        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
-}
-
-static inline void invalidate_dcache(void *address, size_t size)
-{
-        const uintptr_t addr = (uintptr_t)address;
-        /* DCIMVAC - invalidate by address to the point of coherence */
-        for (uintptr_t a = addr; a < addr + size; a += 4) {
-                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
-        }
-}
-
 static inline void clean_dcache_poc(void *address, size_t size)
 {
         const uintptr_t addr = (uintptr_t)address;
-        /* DCCMVAC - clean by address to the point of coherence */
         for (uintptr_t a = addr; a < addr + size; a += 4) {
+                /* DCCMVAC - clean by address to the point of coherence */
                 asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
         }
@@ -82 +66 @@
 void bootstrap(void)
 {
-        /* Make sure  we run in memory code when caches are enabled,
-         * make sure we read memory data too. This part is ARMv7 specific as
-         * ARMv7 no longer invalidates caches on restart.
-         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
-        invalidate_icache();
-        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
-
         /* Enable MMU and caches */
         mmu_start();
@@ -105 +82 @@
                     components[i].start, components[i].name, components[i].inflated,
                     components[i].size);
-                invalidate_dcache(components[i].start, components[i].size);
         }
         
@@ -148 +124 @@
                         halt();
                 }
+                /* Make sure data are in the memory, ICache will need them */
                 clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
         }

boot/arch/arm32/src/mm.c

@@ -37 +37 @@
 #include <arch/asm.h>
 #include <arch/mm.h>
+#include <arch/cp15.h>
+
+#ifdef PROCESSOR_ARCH_armv7_a
+static unsigned log2(unsigned val)
+{
+        unsigned log = 0;
+        while (val >> log++);
+        return log - 2;
+}
+
+static void dcache_invalidate_level(unsigned level)
+{
+        CSSELR_write(level << 1);
+        const uint32_t ccsidr = CCSIDR_read();
+        const unsigned sets = CCSIDR_SETS(ccsidr);
+        const unsigned ways = CCSIDR_WAYS(ccsidr);
+        const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr);
+        const unsigned set_shift = line_log;
+        const unsigned way_shift = 32 - log2(ways);
+
+        for (unsigned k = 0; k < ways; ++k)
+                for (unsigned j = 0; j < sets; ++j) {
+                        const uint32_t val = (level << 1) |
+                            (j << set_shift) | (k << way_shift);
+                        DCISW_write(val);
+                }
+}
+
+/** invalidate all dcaches -- armv7 */
+static void cache_invalidate(void)
+{
+        const uint32_t cinfo = CLIDR_read();
+        for (unsigned i = 0; i < 7; ++i) {
+                switch (CLIDR_CACHE(i, cinfo))
+                {
+                case CLIDR_DCACHE_ONLY:
+                case CLIDR_SEP_CACHE:
+                case CLIDR_UNI_CACHE:
+                        dcache_invalidate_level(i);
+                }
+        }
+        asm volatile ( "dsb\n" );
+        ICIALLU_write(0);
+        asm volatile ( "isb\n" );
+}
+#endif
 
 /** Disable the MMU */
@@ -60 +106 @@
 static inline int section_cacheable(pfn_t section)
 {
+        const unsigned long address = section << PTE_SECTION_SHIFT;
 #ifdef MACHINE_gta02
-        unsigned long address = section << PTE_SECTION_SHIFT;
-
-        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
-                return 0;
-        else
+        if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END)
                 return 1;
 #elif defined MACHINE_beagleboardxm
-        const unsigned long address = section << PTE_SECTION_SHIFT;
         if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
                 return 1;
 #elif defined MACHINE_beaglebone
-        const unsigned long address = section << PTE_SECTION_SHIFT;
         if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
                 return 1;
 #elif defined MACHINE_raspberrypi
-        const unsigned long address = section << PTE_SECTION_SHIFT;
         if (address < BCM2835_RAM_END)
                 return 1;
 #endif
-        return 0;
+        return address * 0;
 }
 
@@ -99 +139 @@
 {
         pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
-        pte->bufferable = 1;
-        pte->cacheable = section_cacheable(frame);
         pte->xn = 0;
         pte->domain = 0;
         pte->should_be_zero_1 = 0;
         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
+#ifdef PROCESSOR_ARCH_armv7_a
+        /*
+         * Keeps this setting in sync with memory type attributes in:
+         * init_boot_pt (boot/arch/arm32/src/mm.c)
+         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+         */
+        pte->tex = section_cacheable(frame) ? 5 : 0;
+        pte->cacheable = section_cacheable(frame) ? 0 : 0;
+        pte->bufferable = section_cacheable(frame) ? 1 : 0;
+#else
+        pte->bufferable = 1;
+        pte->cacheable = section_cacheable(frame);
         pte->tex = 0;
+#endif
         pte->access_permission_1 = 0;
         pte->shareable = 0;
@@ -117 +169 @@
 static void init_boot_pt(void)
 {
-#if defined MACHINE_raspberrypi
-        const pfn_t split_page = 2048;
-#else
-        const pfn_t split_page = PTL0_ENTRIES;
-#endif
-
-        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
-        pfn_t page;
-        for (page = 0; page < split_page; page++)
+        /*
+         * Create 1:1 virtual-physical mapping.
+         * Physical memory on BBxM a BBone starts at 2GB
+         * boundary, icp has a memory mirror at 2GB.
+         * (ARM Integrator Core Module User guide ch. 6.3,  p. 6-7)
+         * gta02 somehow works (probably due to limited address size),
+         * s3c2442b manual ch. 5, p.5-1:
+         * "Address space: 128Mbytes per bank (total 1GB/8 banks)"
+         */
+        for (pfn_t page = 0; page < PTL0_ENTRIES; ++page)
                 init_ptl0_section(&boot_pt[page], page);
 
-#if defined MACHINE_raspberrypi
-        for (; page < PTL0_ENTRIES; page++)
-                init_ptl0_section(&boot_pt[page], page - split_page);
-#endif  
-        asm volatile (
-                "mcr p15, 0, %[pt], c2, c0, 0\n"
-                :: [pt] "r" (boot_pt)
-        );
+        /*
+         * Tell MMU page might be cached. Keeps this setting in sync
+         * with memory type attributes in:
+         * init_ptl0_section (boot/arch/arm32/src/mm.c)
+         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+         */
+        uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
 }
 
@@ -154 +209 @@
                  * we disable caches before jumping to kernel
                  * so this is safe for all archs.
+                 * Enable VMSAv6 the bit (23) is only writable on ARMv6.
+                 * (and QEMU)
                  */
+#ifdef PROCESSOR_ARCH_armv6
+                "ldr r1, =0x00801805\n"
+#else
                 "ldr r1, =0x00001805\n"
+#endif
                 
                 "orr r0, r0, r1\n"
@@ -173 +234 @@
 void mmu_start() {
         disable_paging();
+#ifdef PROCESSOR_ARCH_armv7_a
+        /* Make sure we run in memory code when caches are enabled,
+         * make sure we read memory data too. This part is ARMv7 specific as
+         * ARMv7 no longer invalidates caches on restart.
+         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
+        cache_invalidate();
+#endif
         init_boot_pt();
         enable_paging();