Changeset dc0b964 in mainline for kernel/arch/ia32


Ignore:
Timestamp:
2010-11-24T14:23:14Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
85369b1, b89e1d3
Parents:
8b3bff5
Message:
  • do not hardwire PRI??? formatting macros in the sources, use autotool to detect the correct values
  • use autotool to detect correct values for integer literal macros (UINT32_C, etc.)
  • start using portable UINT??_C style macros for integer constants
Location:
kernel/arch/ia32
Files:
22 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/ia32/include/boot/boot.h

    r8b3bff5 rdc0b964  
    3838#define BOOT_OFFSET      0x108000
    3939#define AP_BOOT_OFFSET   0x8000
    40 #define BOOT_STACK_SIZE  0x400
     40#define BOOT_STACK_SIZE  0x0400
    4141
    4242#define MULTIBOOT_HEADER_MAGIC  0x1BADB002

  • kernel/arch/ia32/include/boot/memmap.h

    r8b3bff5 rdc0b964  
    7070
    7171extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    72 extern uint8_t e820counter; 
     72extern uint8_t e820counter;
    7373
    7474#endif

  • kernel/arch/ia32/include/context.h

    r8b3bff5 rdc0b964  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    4040#include <typedefs.h>
    4141
    42 #define STACK_ITEM_SIZE 4
     42#define STACK_ITEM_SIZE  4
    4343
    4444/*
    … …  
    4848 * One item is put onto stack to support get_stack_base().
    4949 */
    50 #define SP_DELTA        (8 + STACK_ITEM_SIZE)
     50#define SP_DELTA  (8 + STACK_ITEM_SIZE)
    5151
    5252#define context_set(c, _pc, stack, size) \

  • kernel/arch/ia32/include/context_offset.h

    r8b3bff5 rdc0b964  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CONTEXT_OFFSET_H_
    3737
    38 #define OFFSET_SP  0x0
    39 #define OFFSET_PC  0x4
    40 #define OFFSET_EBX 0x8
    41 #define OFFSET_ESI 0xC
    42 #define OFFSET_EDI 0x10
    43 #define OFFSET_EBP 0x14
     38#define OFFSET_SP   0x00
     39#define OFFSET_PC   0x04
     40#define OFFSET_EBX  0x08
     41#define OFFSET_ESI  0x0C
     42#define OFFSET_EDI  0x10
     43#define OFFSET_EBP  0x14
    4444
    45 #ifdef KERNEL 
    46 # define OFFSET_IPL 0x18
     45#ifdef KERNEL
     46        #define OFFSET_IPL 0x18
    4747#else
    48 # define OFFSET_TLS 0x18
     48        #define OFFSET_TLS 0x18
    4949#endif
    5050
     51#ifdef __ASM__
    5152
    52 #ifdef __ASM__
    53 
    54 # ctx: address of the structure with saved context
     53# ctx: address of the structure with saved context
    5554# pc: return address
    5655
    5756.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    58         movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp       
     57        movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp
    5958        movl \pc,OFFSET_PC(\ctx)        # %eip -> ctx->pc
    60         movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx     
    61         movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi     
    62         movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi     
    63         movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp     
     59        movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx
     60        movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi
     61        movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi
     62        movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp
    6463.endm
    6564
    66 # ctx: address of the structure with saved context 
     65# ctx: address of the structure with saved context
    6766
    6867.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    … …  
    7574.endm
    7675
    77 #endif /* __ASM__ */ 
     76#endif /* __ASM__ */
    7877
    7978#endif
    … …  
    8180/** @}
    8281 */
    83 

  • kernel/arch/ia32/include/cpu.h

    r8b3bff5 rdc0b964  
    4444
    4545/* Support for SYSENTER and SYSEXIT */
    46 #define IA32_MSR_SYSENTER_CS    0x174
    47 #define IA32_MSR_SYSENTER_ESP   0x175
    48 #define IA32_MSR_SYSENTER_EIP   0x176
     46#define IA32_MSR_SYSENTER_CS   0x174U
     47#define IA32_MSR_SYSENTER_ESP  0x175U
     48#define IA32_MSR_SYSENTER_EIP  0x176U
    4949
    5050#ifndef __ASM__

  • kernel/arch/ia32/include/drivers/i8259.h

    r8b3bff5 rdc0b964  
    3939#include <arch/interrupt.h>
    4040
    41 #define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
    42 #define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
    43 #define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
    44 #define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
     41#define PIC_PIC0PORT1  ((ioport8_t *) 0x20U)
     42#define PIC_PIC0PORT2  ((ioport8_t *) 0x21U)
     43#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0U)
     44#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1U)
    4545
    4646#define PIC_NEEDICW4  (1 << 0)

  • kernel/arch/ia32/include/istate.h

    r8b3bff5 rdc0b964  
    3737
    3838#ifdef KERNEL
     39
    3940#include <typedefs.h>
    4041#include <trace.h>
    41 #else
     42
     43#else /* KERNEL */
     44
    4245#include <sys/types.h>
     46
    4347#define NO_TRACE
    44 #endif
     48
     49#endif /* KERNEL */
    4550
    4651typedef struct istate {
    … …  
    7782NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    7883{
    79         return !(istate->eip & 0x80000000);
     84        return !(istate->eip & UINT32_C(0x80000000));
    8085}
    8186

  • kernel/arch/ia32/include/mm/as.h

    r8b3bff5 rdc0b964  
    3636#define KERN_ia32_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH         ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH           ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH           ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH             ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    45 #define USTACK_ADDRESS_ARCH     (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
     45#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
    4646
    4747typedef struct {
    … …  
    5050#include <genarch/mm/as_pt.h>
    5151
    52 #define as_constructor_arch(as, flags)          (as != as)
    53 #define as_destructor_arch(as)                  (as != as)
    54 #define as_create_arch(as, flags)               (as != as)
     52#define as_constructor_arch(as, flags)  (as != as)
     53#define as_destructor_arch(as)          (as != as)
     54#define as_create_arch(as, flags)       (as != as)
    5555#define as_install_arch(as)
    5656#define as_deinstall_arch(as)

  • kernel/arch/ia32/include/mm/page.h

    r8b3bff5 rdc0b964  
    3939#include <trace.h>
    4040
    41 #define PAGE_WIDTH      FRAME_WIDTH
    42 #define PAGE_SIZE       FRAME_SIZE
     41#define PAGE_WIDTH  FRAME_WIDTH
     42#define PAGE_SIZE   FRAME_SIZE
    4343
    4444#ifdef KERNEL
    4545
    4646#ifndef __ASM__
    47 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    48 #       define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
    49 #else
    50 #       define KA2PA(x) ((x) - 0x80000000)
    51 #       define PA2KA(x) ((x) + 0x80000000)
    52 #endif
     47
     48#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     49#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
     50
     51#else /* __ASM__ */
     52
     53#define KA2PA(x)  ((x) - 0x80000000)
     54#define PA2KA(x)  ((x) + 0x80000000)
     55
     56#endif /* __ASM__ */
    5357
    5458/*
    … …  
    5862
    5963/* Number of entries in each level. */
    60 #define PTL0_ENTRIES_ARCH       1024
    61 #define PTL1_ENTRIES_ARCH       0
    62 #define PTL2_ENTRIES_ARCH       0
    63 #define PTL3_ENTRIES_ARCH       1024
     64#define PTL0_ENTRIES_ARCH  1024
     65#define PTL1_ENTRIES_ARCH  0
     66#define PTL2_ENTRIES_ARCH  0
     67#define PTL3_ENTRIES_ARCH  1024
    6468
    6569/* Page table sizes for each level. */
    66 #define PTL0_SIZE_ARCH          ONE_FRAME
    67 #define PTL1_SIZE_ARCH          0
    68 #define PTL2_SIZE_ARCH          0
    69 #define PTL3_SIZE_ARCH          ONE_FRAME
     70#define PTL0_SIZE_ARCH  ONE_FRAME
     71#define PTL1_SIZE_ARCH  0
     72#define PTL2_SIZE_ARCH  0
     73#define PTL3_SIZE_ARCH  ONE_FRAME
    7074
    7175/* Macros calculating indices for each level. */
    72 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    73 #define PTL1_INDEX_ARCH(vaddr)  0
    74 #define PTL2_INDEX_ARCH(vaddr)  0
    75 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     76#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
     77#define PTL1_INDEX_ARCH(vaddr)  0
     78#define PTL2_INDEX_ARCH(vaddr)  0
     79#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7680
    7781/* Get PTE address accessors for each level. */
    … …  
    122126#define PTE_WRITABLE_ARCH(p) \
    123127        ((p)->writeable != 0)
    124 #define PTE_EXECUTABLE_ARCH(p)                  1
     128#define PTE_EXECUTABLE_ARCH(p)  1
    125129
    126130#ifndef __ASM__
    … …  
    144148
    145149/** When bit on this position is 1, a reserved bit was set in page directory. */
    146 #define PFERR_CODE_RSVD         (1 << 3)       
     150#define PFERR_CODE_RSVD         (1 << 3)
    147151
    148152/** Page Table Entry. */

  • kernel/arch/ia32/include/smp/ap.h

    r8b3bff5 rdc0b964  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */

  • kernel/arch/ia32/include/smp/apic.h

    r8b3bff5 rdc0b964  
    4949
    5050/** Delivery modes. */
    51 #define DELMOD_FIXED    0x0
    52 #define DELMOD_LOWPRI   0x1
    53 #define DELMOD_SMI      0x2
     51#define DELMOD_FIXED    0x0U
     52#define DELMOD_LOWPRI   0x1U
     53#define DELMOD_SMI      0x2U
    5454/* 0x3 reserved */
    55 #define DELMOD_NMI      0x4
    56 #define DELMOD_INIT     0x5
    57 #define DELMOD_STARTUP  0x6
    58 #define DELMOD_EXTINT   0x7
     55#define DELMOD_NMI      0x4U
     56#define DELMOD_INIT     0x5U
     57#define DELMOD_STARTUP  0x6U
     58#define DELMOD_EXTINT   0x7U
    5959
    6060/** Destination modes. */
    61 #define DESTMOD_PHYS   0x0
    62 #define DESTMOD_LOGIC  0x1
     61#define DESTMOD_PHYS   0x0U
     62#define DESTMOD_LOGIC  0x1U
    6363
    6464/** Trigger Modes. */
    65 #define TRIGMOD_EDGE   0x0
    66 #define TRIGMOD_LEVEL  0x1
     65#define TRIGMOD_EDGE   0x0U
     66#define TRIGMOD_LEVEL  0x1U
    6767
    6868/** Levels. */
    69 #define LEVEL_DEASSERT  0x0
    70 #define LEVEL_ASSERT    0x1
     69#define LEVEL_DEASSERT  0x0U
     70#define LEVEL_ASSERT    0x1U
    7171
    7272/** Destination Shorthands. */
    73 #define SHORTHAND_NONE      0x0
    74 #define SHORTHAND_SELF      0x1
    75 #define SHORTHAND_ALL_INCL  0x2
    76 #define SHORTHAND_ALL_EXCL  0x3
     73#define SHORTHAND_NONE      0x0U
     74#define SHORTHAND_SELF      0x1U
     75#define SHORTHAND_ALL_INCL  0x2U
     76#define SHORTHAND_ALL_EXCL  0x3U
    7777
    7878/** Interrupt Input Pin Polarities. */
    79 #define POLARITY_HIGH  0x0
    80 #define POLARITY_LOW   0x1
     79#define POLARITY_HIGH  0x0U
     80#define POLARITY_LOW   0x1U
    8181
    8282/** Divide Values. (Bit 2 is always 0) */
    83 #define DIVIDE_2    0x0
    84 #define DIVIDE_4    0x1
    85 #define DIVIDE_8    0x2
    86 #define DIVIDE_16   0x3
    87 #define DIVIDE_32   0x8
    88 #define DIVIDE_64   0x9
    89 #define DIVIDE_128  0xa
    90 #define DIVIDE_1    0xb
     83#define DIVIDE_2    0x0U
     84#define DIVIDE_4    0x1U
     85#define DIVIDE_8    0x2U
     86#define DIVIDE_16   0x3U
     87#define DIVIDE_32   0x8U
     88#define DIVIDE_64   0x9U
     89#define DIVIDE_128  0xaU
     90#define DIVIDE_1    0xbU
    9191
    9292/** Timer Modes. */
    93 #define TIMER_ONESHOT   0x0
    94 #define TIMER_PERIODIC  0x1
     93#define TIMER_ONESHOT   0x0U
     94#define TIMER_PERIODIC  0x1U
    9595
    9696/** Delivery status. */
    97 #define DELIVS_IDLE     0x0
    98 #define DELIVS_PENDING  0x1
     97#define DELIVS_IDLE     0x0U
     98#define DELIVS_PENDING  0x1U
    9999
    100100/** Destination masks. */
    101 #define DEST_ALL  0xff
     101#define DEST_ALL  0xffU
    102102
    103103/** Dest format models. */
    104 #define MODEL_FLAT     0xf
    105 #define MODEL_CLUSTER  0x0
     104#define MODEL_FLAT     0xfU
     105#define MODEL_CLUSTER  0x0U
    106106
    107107/** Interrupt Command Register. */
    108 #define ICRlo  (0x300 / sizeof(uint32_t))
    109 #define ICRhi  (0x310 / sizeof(uint32_t))
     108#define ICRlo  (0x300U / sizeof(uint32_t))
     109#define ICRhi  (0x310U / sizeof(uint32_t))
    110110
    111111typedef struct {
    … …  
    135135
    136136/* End Of Interrupt. */
    137 #define EOI  (0x0b0 / sizeof(uint32_t))
     137#define EOI  (0x0b0U / sizeof(uint32_t))
    138138
    139139/** Error Status Register. */
    140 #define ESR  (0x280 / sizeof(uint32_t))
     140#define ESR  (0x280U / sizeof(uint32_t))
    141141
    142142typedef union {
    … …  
    157157
    158158/* Task Priority Register */
    159 #define TPR  (0x080 / sizeof(uint32_t))
     159#define TPR  (0x080U / sizeof(uint32_t))
    160160
    161161typedef union {
    … …  
    168168
    169169/** Spurious-Interrupt Vector Register. */
    170 #define SVR  (0x0f0 / sizeof(uint32_t))
     170#define SVR  (0x0f0U / sizeof(uint32_t))
    171171
    172172typedef union {
    … …  
    181181
    182182/** Time Divide Configuration Register. */
    183 #define TDCR  (0x3e0 / sizeof(uint32_t))
     183#define TDCR  (0x3e0U / sizeof(uint32_t))
    184184
    185185typedef union {
    … …  
    192192
    193193/* Initial Count Register for Timer */
    194 #define ICRT  (0x380 / sizeof(uint32_t))
     194#define ICRT  (0x380U / sizeof(uint32_t))
    195195
    196196/* Current Count Register for Timer */
    197 #define CCRT  (0x390 / sizeof(uint32_t))
     197#define CCRT  (0x390U / sizeof(uint32_t))
    198198
    199199/** LVT Timer register. */
    200 #define LVT_Tm  (0x320 / sizeof(uint32_t))
     200#define LVT_Tm  (0x320U / sizeof(uint32_t))
    201201
    202202typedef union {
    … …  
    214214
    215215/** LVT LINT registers. */
    216 #define LVT_LINT0  (0x350 / sizeof(uint32_t))
    217 #define LVT_LINT1  (0x360 / sizeof(uint32_t))
     216#define LVT_LINT0  (0x350U / sizeof(uint32_t))
     217#define LVT_LINT1  (0x360U / sizeof(uint32_t))
    218218
    219219typedef union {
    … …  
    233233
    234234/** LVT Error register. */
    235 #define LVT_Err  (0x370 / sizeof(uint32_t))
     235#define LVT_Err  (0x370U / sizeof(uint32_t))
    236236
    237237typedef union {
    … …  
    248248
    249249/** Local APIC ID Register. */
    250 #define L_APIC_ID  (0x020 / sizeof(uint32_t))
     250#define L_APIC_ID  (0x020U / sizeof(uint32_t))
    251251
    252252typedef union {
    … …  
    259259
    260260/** Local APIC Version Register */
    261 #define LAVR       (0x030 / sizeof(uint32_t))
    262 #define LAVR_Mask  0xff
    263 
    264 #define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
    265 #define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
    266 #define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
     261#define LAVR       (0x030U / sizeof(uint32_t))
     262#define LAVR_Mask  0xffU
     263
     264#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
     265#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
     266#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
    267267
    268268/** Logical Destination Register. */
    269 #define  LDR  (0x0d0 / sizeof(uint32_t))
     269#define  LDR  (0x0d0U / sizeof(uint32_t))
    270270
    271271typedef union {
    … …  
    278278
    279279/** Destination Format Register. */
    280 #define DFR  (0x0e0 / sizeof(uint32_t))
     280#define DFR  (0x0e0U / sizeof(uint32_t))
    281281
    282282typedef union {
    … …  
    289289
    290290/* IO APIC */
    291 #define IOREGSEL  (0x00 / sizeof(uint32_t))
    292 #define IOWIN     (0x10 / sizeof(uint32_t))
    293 
    294 #define IOAPICID   0x00
    295 #define IOAPICVER  0x01
    296 #define IOAPICARB  0x02
    297 #define IOREDTBL   0x10
     291#define IOREGSEL  (0x00U / sizeof(uint32_t))
     292#define IOWIN     (0x10U / sizeof(uint32_t))
     293
     294#define IOAPICID   0x00U
     295#define IOAPICVER  0x01U
     296#define IOAPICARB  0x02U
     297#define IOREDTBL   0x10U
    298298
    299299/** I/O Register Select Register. */

  • kernel/arch/ia32/include/types.h

    r8b3bff5 rdc0b964  
    5050} fncptr_t;
    5151
    52 #define PRIp "x"  /**< Format for uintptr_t. */
    53 #define PRIs "u"  /**< Format for size_t. */
    54 
    55 #define PRId8 "d"     /**< Format for int8_t. */
    56 #define PRId16 "d"    /**< Format for int16_t. */
    57 #define PRId32 "d"    /**< Format for int32_t. */
    58 #define PRId64 "lld"  /**< Format for int64_t. */
    59 #define PRIdn "d"     /**< Format for native_t. */
    60 
    61 #define PRIu8 "u"     /**< Format for uint8_t. */
    62 #define PRIu16 "u"    /**< Format for uint16_t. */
    63 #define PRIu32 "u"    /**< Format for uint32_t. */
    64 #define PRIu64 "llu"  /**< Format for uint64_t. */
    65 #define PRIun "u"     /**< Format for unative_t. */
    66 
    67 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    68 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    69 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    70 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    71 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     52#define PRIp   PRIx32  /**< Format for uintptr_t. */
     53#define PRIs   PRIu32  /**< Format for size_t. */
     54#define PRIdn  PRId32  /**< Format for native_t. */
     55#define PRIun  PRIu32  /**< Format for unative_t. */
     56#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7257
    7358#endif

  • kernel/arch/ia32/src/bios/bios.c

    r8b3bff5 rdc0b964  
    3636#include <typedefs.h>
    3737
    38 #define BIOS_EBDA_PTR  0x40e
     38#define BIOS_EBDA_PTR  0x40eU
    3939
    4040uintptr_t ebda = 0;
    … …  
    4343{
    4444        /* Copy the EBDA address out from BIOS Data Area */
    45         ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
     45        ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U;
    4646}
    4747

  • kernel/arch/ia32/src/boot/memmap.c

    r8b3bff5 rdc0b964  
    3535#include <arch/boot/memmap.h>
    3636
    37 uint8_t e820counter = 0xff;
     37uint8_t e820counter = 0xffU;
    3838e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    3939

  • kernel/arch/ia32/src/cpu/cpu.c

    r8b3bff5 rdc0b964  
    4949 * Contains only non-MP-Specification specific SMP code.
    5050 */
    51 #define AMD_CPUID_EBX  0x68747541
    52 #define AMD_CPUID_ECX  0x444d4163
    53 #define AMD_CPUID_EDX  0x69746e65
     51#define AMD_CPUID_EBX  UINT32_C(0x68747541)
     52#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
     53#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
    5454
    55 #define INTEL_CPUID_EBX  0x756e6547
    56 #define INTEL_CPUID_ECX  0x6c65746e
    57 #define INTEL_CPUID_EDX  0x49656e69
     55#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
     56#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
     57#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
    5858
    5959
    … …  
    140140                if ((info.cpuid_ebx == AMD_CPUID_EBX)
    141141                    && (info.cpuid_ecx == AMD_CPUID_ECX)
    142                         && (info.cpuid_edx == AMD_CPUID_EDX))
     142                    && (info.cpuid_edx == AMD_CPUID_EDX))
    143143                        CPU->arch.vendor = VendorAMD;
    144144               
    145145                /*
    146146                 * Check for Intel processor.
    147                  */             
     147                 */
    148148                if ((info.cpuid_ebx == INTEL_CPUID_EBX)
    149149                    && (info.cpuid_ecx == INTEL_CPUID_ECX)
    150                         && (info.cpuid_edx == INTEL_CPUID_EDX))
     150                    && (info.cpuid_edx == INTEL_CPUID_EDX))
    151151                        CPU->arch.vendor = VendorIntel;
    152152               
    153153                cpuid(INTEL_CPUID_STANDARD, &info);
    154                 CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
    155                 CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
    156                 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                                             
     154                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU;
     155                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU;
     156                CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU;
    157157        }
    158158}

  • kernel/arch/ia32/src/debug/stacktrace.c

    r8b3bff5 rdc0b964  
    3737#include <typedefs.h>
    3838
    39 #define FRAME_OFFSET_FP_PREV    0
    40 #define FRAME_OFFSET_RA         1
     39#define FRAME_OFFSET_FP_PREV  0
     40#define FRAME_OFFSET_RA       1
    4141
    4242bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)

  • kernel/arch/ia32/src/drivers/i8254.c

    r8b3bff5 rdc0b964  
    5454#include <ddi/device.h>
    5555
    56 #define CLK_PORT1  ((ioport8_t *) 0x40)
    57 #define CLK_PORT4  ((ioport8_t *) 0x43)
     56#define CLK_PORT1  ((ioport8_t *) 0x40U)
     57#define CLK_PORT4  ((ioport8_t *) 0x43U)
    5858
    5959#define CLK_CONST     1193180

  • kernel/arch/ia32/src/drivers/i8259.c

    r8b3bff5 rdc0b964  
    121121void pic_eoi(void)
    122122{
    123         pio_write_8((ioport8_t *)0x20, 0x20);
    124         pio_write_8((ioport8_t *)0xa0, 0x20);
     123        pio_write_8((ioport8_t *) 0x20, 0x20);
     124        pio_write_8((ioport8_t *) 0xa0, 0x20);
    125125}
    126126

  • kernel/arch/ia32/src/drivers/vesa.c

    r8b3bff5 rdc0b964  
    7070bool vesa_init(void)
    7171{
    72         if ((vesa_width == 0xffff) || (vesa_height == 0xffff))
     72        if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU))
    7373                return false;
    7474       

  • kernel/arch/ia32/src/mm/frame.c

    r8b3bff5 rdc0b964  
    4444#include <align.h>
    4545#include <macros.h>
    46 
    4746#include <print.h>
    4847
    49 #define PHYSMEM_LIMIT32  0x07c000000ull
    50 #define PHYSMEM_LIMIT64  0x200000000ull
     48#define PHYSMEM_LIMIT32  UINT64_C(0x07c000000)
     49#define PHYSMEM_LIMIT64  UINT64_C(0x200000000)
    5150
    5251size_t hardcoded_unmapped_ktext_size = 0;

  • kernel/arch/ia32/src/smp/apic.c

    r8b3bff5 rdc0b964  
    7272 *
    7373 */
    74 volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
    75 volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
     74volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
     75volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
    7676
    7777uint32_t apic_id_mask = 0;
    … …  
    184184         * Other interrupts will be forwarded to the lowest priority CPU.
    185185         */
    186         io_apic_disable_irqs(0xffff);
     186        io_apic_disable_irqs(0xffffU);
    187187       
    188188        irq_initialize(&l_apic_timer_irq);

  • kernel/arch/ia32/src/smp/mps.c

    r8b3bff5 rdc0b964  
    5252 */
    5353
    54 #define FS_SIGNATURE  0x5f504d5f
    55 #define CT_SIGNATURE  0x504d4350
     54#define FS_SIGNATURE  UINT32_C(0x5f504d5f)
     55#define CT_SIGNATURE  UINT32_C(0x504d4350)
    5656
    5757static struct mps_fs *fs;
Note: See TracChangeset for help on using the changeset viewer.