Changeset d6f9fff in mainline for kernel/arch/ia32/src/pm.c


Ignore:
Timestamp:
2016-04-27T12:39:14Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
1a5eca4
Parents:
8a36bc1e
Message:

ia32: Make TLS settable from uspace

The TLS document[1] mandates that %gs[0] is the thread pointer on ia32.
That is good as it allows userspace-only TLS management for fibrils:
fibril_save/restore() simply manipulate the thread pointer in %gs:0 and
don't need to ask the kernel to modify %gs's base. The kernel treats
%gs:0 as another preserved register and preserves it across context
switches. GCC gets in the way a little bit because it by default assumes
that TLS is accessible from negative %gs offsets (which would
necessitate a kernel-assisted solution). Fortunately, there is a GCC
option to suppress this assumption.

  • Introduce the concept of virtual registers, with VREG_TP (thread pointer) being the first of them
  • Preserve VREG_TP in context_save/restore()
  • Stop using sys_tls_set() in favour of using %gs:0 as the thread pointer
  • Make GCC generate code that always goes through %gs:0 to access TLS

[1] Drepper, U.: ELF Handling For Thread-Local Storage

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/src/pm.c

    r8a36bc1e rd6f9fff  
    4141#include <panic.h>
    4242#include <arch/mm/page.h>
     43#include <mm/km.h>
     44#include <mm/frame.h>
    4345#include <mm/slab.h>
    4446#include <memstr.h>
     
    5153
    5254/*
    53  * We have no use for segmentation so we set up flat mode. In this
    54  * mode, we use, for each privilege level, two segments spanning the
     55 * We don't have much use for segmentation so we set up flat mode.
     56 * In this mode, we use, for each privilege level, two segments spanning the
    5557 * whole memory. One is for code and one is for data.
    5658 *
    57  * One is for GS register which holds pointer to the TLS thread
    58  * structure in it's base.
     59 * One special segment apart of that is for the GS register which holds
     60 * a pointer to the VREG page in its base.
    5961 */
    6062descriptor_t gdt[GDT_ITEMS] = {
     
    7173        /* TSS descriptor - set up will be completed later */
    7274        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    73         /* TLS descriptor */
    74         { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
     75        /* VREG descriptor - segment used for virtual registers, will be reinitialized later */
     76        { 0xffff, 0 , 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
    7577        /* VESA Init descriptor */
    7678#ifdef CONFIG_FB
     
    8284static idescriptor_t idt[IDT_ITEMS];
    8385
    84 static tss_t tss;
     86static tss_t tss0;
    8587
    8688tss_t *tss_p = NULL;
     
    9597{
    9698        d->base_0_15 = base & 0xffff;
    97         d->base_16_23 = ((base) >> 16) & 0xff;
    98         d->base_24_31 = ((base) >> 24) & 0xff;
     99        d->base_16_23 = (base >> 16) & 0xff;
     100        d->base_24_31 = (base >> 24) & 0xff;
    99101}
    100102
     
    265267                 * the heap hasn't been initialized so far.
    266268                 */
    267                 tss_p = &tss;
    268         }
    269         else {
     269                tss_p = &tss0;
     270        } else {
    270271                tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
    271272                if (!tss_p)
     
    292293}
    293294
    294 void set_tls_desc(uintptr_t tls)
    295 {
    296         ptr_16_32_t cpugdtr;
    297         descriptor_t *gdt_p;
    298 
    299         gdtr_store(&cpugdtr);
    300         gdt_p = (descriptor_t *) cpugdtr.base;
    301         gdt_setbase(&gdt_p[TLS_DES], tls);
    302         /* Reload gdt register to update GS in CPU */
    303         gdtr_load(&cpugdtr);
    304 }
    305 
    306295/** @}
    307296 */
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