Changeset d6f9fff in mainline for kernel/arch/ia32/src/pm.c

Timestamp:

2016-04-27T12:39:14Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1a5eca4

Parents:

8a36bc1e

Message:

ia32: Make TLS settable from uspace

The TLS document[1] mandates that %gs[0] is the thread pointer on ia32.
That is good as it allows userspace-only TLS management for fibrils:
fibril_save/restore() simply manipulate the thread pointer in %gs:0 and
don't need to ask the kernel to modify %gs's base. The kernel treats
%gs:0 as another preserved register and preserves it across context
switches. GCC gets in the way a little bit because it by default assumes
that TLS is accessible from negative %gs offsets (which would
necessitate a kernel-assisted solution). Fortunately, there is a GCC
option to suppress this assumption.

• Introduce the concept of virtual registers, with VREG_TP (thread pointer) being the first of them
• Preserve VREG_TP in context_save/restore()
• Stop using sys_tls_set() in favour of using %gs:0 as the thread pointer
• Make GCC generate code that always goes through %gs:0 to access TLS

[1] Drepper, U.: ELF Handling For Thread-Local Storage

File:

• kernel/arch/ia32/src/pm.c (modified) (7 diffs)

kernel/arch/ia32/src/pm.c

@@ -41 +41 @@
 #include <panic.h>
 #include <arch/mm/page.h>
+#include <mm/km.h>
+#include <mm/frame.h>
 #include <mm/slab.h>
 #include <memstr.h>
@@ -51 +53 @@
 
 /*
- * We have no use for segmentation so we set up flat mode. In this
- * mode, we use, for each privilege level, two segments spanning the
+ * We don't have much use for segmentation so we set up flat mode.
+ * In this mode, we use, for each privilege level, two segments spanning the
  * whole memory. One is for code and one is for data.
  *
- * One is for GS register which holds pointer to the TLS thread
- * structure in it's base.
+ * One special segment apart of that is for the GS register which holds
+ * a pointer to the VREG page in its base.
  */
 descriptor_t gdt[GDT_ITEMS] = {
@@ -71 +73 @@
         /* TSS descriptor - set up will be completed later */
         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-        /* TLS descriptor */
-        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
+        /* VREG descriptor - segment used for virtual registers, will be reinitialized later */
+        { 0xffff, 0 , 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
         /* VESA Init descriptor */
 #ifdef CONFIG_FB
@@ -82 +84 @@
 static idescriptor_t idt[IDT_ITEMS];
 
-static tss_t tss;
+static tss_t tss0;
 
 tss_t *tss_p = NULL;
@@ -95 +97 @@
 {
         d->base_0_15 = base & 0xffff;
-        d->base_16_23 = ((base) >> 16) & 0xff;
-        d->base_24_31 = ((base) >> 24) & 0xff;
+        d->base_16_23 = (base >> 16) & 0xff;
+        d->base_24_31 = (base >> 24) & 0xff;
 }
 
@@ -265 +267 @@
                  * the heap hasn't been initialized so far.
                  */
-                tss_p = &tss;
-        }
-        else {
+                tss_p = &tss0;
+        } else {
                 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
                 if (!tss_p)
@@ -292 +293 @@
 }
 
-void set_tls_desc(uintptr_t tls)
-{
-        ptr_16_32_t cpugdtr;
-        descriptor_t *gdt_p;
-
-        gdtr_store(&cpugdtr);
-        gdt_p = (descriptor_t *) cpugdtr.base;
-        gdt_setbase(&gdt_p[TLS_DES], tls);
-        /* Reload gdt register to update GS in CPU */
-        gdtr_load(&cpugdtr);
-}
-
 /** @}
  */