Changeset d6e5cbc in mainline for arch/ia32/include/barrier.h


Ignore:
Timestamp:
2006-05-28T18:17:36Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5552d60
Parents:
3bf5976
Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/barrier.h

    r3bf5976 rd6e5cbc  
    3030#define __ia32_BARRIER_H__
    3131
    32 #include <arch/types.h>
    33 
    3432/*
    3533 * NOTE:
    … …  
    6159#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
    6260#       else
    63 #               define write_barrier()
     61#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    6462#       endif
    6563#elif CONFIG_FENCES_P3
    … …  
    6967#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
    7068#       else
    71 #               define write_barrier()
     69#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    7270#       endif
    7371#else
    … …  
    7775#               define write_barrier()  cpuid_serialization()
    7876#       else
    79 #               define write_barrier()
     77#               define write_barrier()  __asm__ volatile( "" ::: "memory");
    8078#       endif
    8179#endif
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