Changeset d6e5cbc in mainline for arch

Timestamp:

2006-05-28T18:17:36Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5552d60

Parents:

3bf5976

Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

Location:

arch

Files:

• ia32/include/barrier.h (modified) (4 diffs)
• mips32/include/barrier.h (modified) (1 diff)
• mips32/include/cp0.h (modified) (1 diff)
• mips32/src/interrupt.c (modified) (2 diffs)
• mips32/src/mips32.c (modified) (3 diffs)

arch/ia32/include/barrier.h

@@ -30 +30 @@
 #define __ia32_BARRIER_H__
 
-#include <arch/types.h>
-
 /*
  * NOTE:
@@ -61 +59 @@
 #               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
 #       else
-#               define write_barrier()
+#               define write_barrier()  __asm__ volatile( "" ::: "memory");
 #       endif
 #elif CONFIG_FENCES_P3
@@ -69 +67 @@
 #               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
 #       else
-#               define write_barrier()
+#               define write_barrier()  __asm__ volatile( "" ::: "memory");
 #       endif
 #else
@@ -77 +75 @@
 #               define write_barrier()  cpuid_serialization()
 #       else
-#               define write_barrier()
+#               define write_barrier()  __asm__ volatile( "" ::: "memory");
 #       endif
 #endif

arch/mips32/include/barrier.h

@@ -36 +36 @@
 #define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
 
-#define memory_barrier()
-#define read_barrier()
-#define write_barrier()
+#define memory_barrier()        __asm__ volatile ("" ::: "memory")
+#define read_barrier()          __asm__ volatile ("" ::: "memory")
+#define write_barrier()         __asm__ volatile ("" ::: "memory")
 
 #endif

arch/mips32/include/cp0.h

@@ -50 +50 @@
 /*
  * Magic value for use in msim.
- * On AMD Duron 800Mhz, this roughly seems like one us.
  */
-#define cp0_compare_value               10000
+#define cp0_compare_value               100000
 
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))

arch/mips32/src/interrupt.c

@@ -77 +77 @@
 }
 
+/* TODO: This is SMP unsafe!!! */
+static unsigned long nextcount;
+/** Start hardware clock */
+static void timer_start(void)
+{
+        nextcount = cp0_compare_value + cp0_count_read();
+        cp0_compare_write(nextcount);
+}
+
 static void timer_exception(int n, istate_t *istate)
 {
-        cp0_compare_write(cp0_count_read() + cp0_compare_value); 
+        unsigned long drift;
+
+        drift = cp0_count_read() - nextcount;
+        while (drift > cp0_compare_value) {
+                drift -= cp0_compare_value;
+                CPU->missed_clock_ticks++;
+        }
+        nextcount = cp0_count_read() + cp0_compare_value - drift;
+        cp0_compare_write(nextcount);
         clock();
 }
@@ -101 +118 @@
         int_register(0, "swint0", swint0);
         int_register(1, "swint1", swint1);
+        timer_start();
 }
 

arch/mips32/src/mips32.c

@@ -81 +81 @@
         /* Initialize dispatch table */
         exception_init();
-        interrupt_init();
-
         arc_init();
 
@@ -90 +88 @@
         memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
+        interrupt_init();
         /*
          * Switch to BEV normal level so that exception vectors point to the kernel.
@@ -100 +99 @@
          */
         cp0_mask_all_int();
+
         /*
          * Unmask hardware clock interrupt.
          */
         cp0_unmask_int(TIMER_IRQ);
-
-        /*
-         * Start hardware clock.
-         */
-        cp0_compare_write(cp0_compare_value + cp0_count_read());
 
         console_init();