Changeset d085df10 in mainline for kernel/arch/arm32/include

Timestamp:

2012-09-23T16:19:26Z (13 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

21aab25

Parents:

47d2ca9 (diff), 40ad375 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

merge changes from the beagleboard-xm branch

Location:

kernel/arch/arm32/include

Files:

• asm.h (modified) (2 diffs)
• barrier.h (modified) (1 diff)
• regutils.h (modified) (1 diff)

kernel/arch/arm32/include/asm.h

@@ -46 +46 @@
  *
  * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
+ * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
+ * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
  */
 NO_TRACE static inline void cpu_sleep(void)
@@ -51 +53 @@
 #ifdef PROCESSOR_armv7_a
         asm volatile ( "wfe" :: );
+#elif defined(MACHINE_gta02)
+        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
 #endif
 }

kernel/arch/arm32/include/barrier.h

@@ -47 +47 @@
 #define write_barrier()   asm volatile ("" ::: "memory")
 
-#define smc_coherence(a)
-#define smc_coherence_block(a, l)
+/*
+ * There are multiple ways ICache can be implemented on ARM machines. Namely
+ * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
+ * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
+ * compatibility across processors, ARM recommends that operating systems target
+ * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
+ * and do not assume the presence of the IVIPT extension. Software that relies
+ * on the IVIPT extension might fail in an unpredictable way on an ARMv7
+ * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
+ * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
+ *
+ * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
+ * maintenance to other places than just smc.
+ */
+
+/* Available on both all supported arms,
+ * invalidates entire ICache so the written value does not matter. */
+#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
+#define smc_coherence_block(a, l) smc_coherence(a)
+
 
 #endif

kernel/arch/arm32/include/regutils.h

@@ -41 +41 @@
 #define STATUS_REG_MODE_MASK         0x1f
 
-#define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
-#define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
-#define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
-#define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
-#define CP15_R1_INST_CACHE_BIT       (1 << 12)
-#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
-#define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
-#define CP15_R1_HA_ENABLE_BIT        (1 << 17)
-#define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
-#define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
-#define CP15_R1_FI_BIT               (1 << 21)
-#define CP15_R1_VE_BIT               (1 << 24)
-#define CP15_R1_EE_BIT               (1 << 25)
-#define CP15_R1_NMFI_BIT             (1 << 27)
-#define CP15_R1_TRE_BIT              (1 << 28)
-#define CP15_R1_AFE_BIT              (1 << 29)
+/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+#define CP15_R1_MMU_EN            (1 << 0)
+#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
+#define CP15_R1_CACHE_EN          (1 << 2)
+#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
+#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
+#define CP15_R1_SWAP_EN           (1 << 10)
+#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
+#define CP15_R1_INST_CACHE_EN     (1 << 12)
+#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
+#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
+#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
+#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
+#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
+#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
+#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
+#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
+#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
+#define CP15_R1_NMFI_EN           (1 << 27)
+#define CP15_R1_TEX_REMAP_EN      (1 << 28)
+#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
+#define CP15_R1_THUMB_EXC_EN      (1 << 30)
 
 /* ARM Processor Operation Modes */