Changeset cade9c1 in mainline for kernel/arch/sparc64/include

Timestamp:

2014-10-30T12:48:50Z (11 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3579629

Parents:

aef669b

Message:

sparc64/sun4v trap overhaul.

• Handle interrupt, MMU and other essential traps via exc_dispatch()
• Handle data_access_exception on TL>1
• Switch the sun4v code to the previously modified istate_t structure

Location:

kernel/arch/sparc64/include/arch

Files:

• mm/sun4v/tlb.h (modified) (1 diff)
• trap/sun4v/interrupt.h (modified) (1 diff)
• trap/sun4v/mmu.h (modified) (4 diffs)

kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h

@@ -141 +141 @@
 }
 
-extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
-extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
-extern void fast_data_access_protection(sysarg_t, istate_t *);
+extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
+extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
+extern void fast_data_access_protection(unsigned int, istate_t *);
 
 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h

@@ -40 +40 @@
 #ifndef __ASM__
 
+#include <arch/istate_struct.h>
+
 extern void sun4v_ipi_init(void);
-extern void cpu_mondo(void);
+extern void cpu_mondo(unsigned int, istate_t *);
 
 #endif

kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

@@ -73 +73 @@
 
 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
-        PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
+        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
+        clr %g5         ! XXX
+        PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 
@@ -123 +125 @@
          * mapped. In such a case, this handler will be called from TL = 1.
          * We handle the situation by pretending that the MMU miss occurred
-         * on TL = 0. Once the MMU miss trap is services, the instruction which
+         * on TL = 0. Once the MMU miss trap is serviced, the instruction which
          * caused the spill/fill trap is restarted, the spill/fill trap occurs,
-         * but this time its handler accesse memory which IS mapped.
+         * but this time its handler accesses memory which is mapped.
          */
         .if (\tl > 0)
@@ -131 +133 @@
         .endif
 
+        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
+
         /*
-         * Save the faulting virtual page and faulting context to the %g2
-         * register. The most significant 51 bits of the %g2 register will
+         * Save the faulting virtual page and faulting context to the %g5
+         * register. The most significant 51 bits of the %g5 register will
          * contain the virtual address which caused the fault truncated to the
-         * page boundary. The least significant 13 bits of the %g2 register
+         * page boundary. The least significant 13 bits of the %g5 register
          * will contain the number of the context in which the fault occurred.
-         * The value of the %g2 register will be passed as a parameter to the
-         * higher level service routine.
+         * The value of the %g5 register will be stored in the istate structure
+         * for inspeciton by the higher level service routine.
          */
-        or %g1, %g3, %g2
+        or %g1, %g3, %g5
 
-        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
+        PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
@@ -170 +174 @@
         sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
 
+        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
+
         /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
-        or %g1, %g3, %g2
+        or %g1, %g3, %g5
 
-        PREEMPTIBLE_HANDLER fast_data_access_protection
+        PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 #endif /* __ASM__ */