Changeset cade9c1 in mainline


Ignore:
Timestamp:
2014-10-30T12:48:50Z (10 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3579629
Parents:
aef669b
Message:

sparc64/sun4v trap overhaul.

  • Handle interrupt, MMU and other essential traps via exc_dispatch()
  • Handle data_access_exception on TL>1
  • Switch the sun4v code to the previously modified istate_t structure
Location:
kernel/arch/sparc64
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h

    raef669b rcade9c1  
    141141}
    142142
    143 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    144 extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
    145 extern void fast_data_access_protection(sysarg_t, istate_t *);
     143extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
     144extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
     145extern void fast_data_access_protection(unsigned int, istate_t *);
    146146
    147147extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h

    raef669b rcade9c1  
    4040#ifndef __ASM__
    4141
     42#include <arch/istate_struct.h>
     43
    4244extern void sun4v_ipi_init(void);
    43 extern void cpu_mondo(void);
     45extern void cpu_mondo(unsigned int, istate_t *);
    4446
    4547#endif

  • kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

    raef669b rcade9c1  
    7373
    7474.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    75         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     75        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     76        clr %g5         ! XXX
     77        PREEMPTIBLE_HANDLER exc_dispatch
    7678.endm
    7779
    … …  
    123125         * mapped. In such a case, this handler will be called from TL = 1.
    124126         * We handle the situation by pretending that the MMU miss occurred
    125          * on TL = 0. Once the MMU miss trap is services, the instruction which
     127         * on TL = 0. Once the MMU miss trap is serviced, the instruction which
    126128         * caused the spill/fill trap is restarted, the spill/fill trap occurs,
    127          * but this time its handler accesse memory which IS mapped.
     129         * but this time its handler accesses memory which is mapped.
    128130         */
    129131        .if (\tl > 0)
    … …  
    131133        .endif
    132134
     135        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     136
    133137        /*
    134          * Save the faulting virtual page and faulting context to the %g2
    135          * register. The most significant 51 bits of the %g2 register will
     138         * Save the faulting virtual page and faulting context to the %g5
     139         * register. The most significant 51 bits of the %g5 register will
    136140         * contain the virtual address which caused the fault truncated to the
    137          * page boundary. The least significant 13 bits of the %g2 register
     141         * page boundary. The least significant 13 bits of the %g5 register
    138142         * will contain the number of the context in which the fault occurred.
    139          * The value of the %g2 register will be passed as a parameter to the
    140          * higher level service routine.
     143         * The value of the %g5 register will be stored in the istate structure
     144         * for inspeciton by the higher level service routine.
    141145         */
    142         or %g1, %g3, %g2
     146        or %g1, %g3, %g5
    143147
    144         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     148        PREEMPTIBLE_HANDLER exc_dispatch
    145149.endm
    146150
    … …  
    170174        sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
    171175
     176        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     177
    172178        /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
    173         or %g1, %g3, %g2
     179        or %g1, %g3, %g5
    174180
    175         PREEMPTIBLE_HANDLER fast_data_access_protection
     181        PREEMPTIBLE_HANDLER exc_dispatch
    176182.endm
    177183#endif /* __ASM__ */

  • kernel/arch/sparc64/src/mm/sun4v/tlb.c

    raef669b rcade9c1  
    208208
    209209/** ITLB miss handler. */
    210 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
     210void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
    211211{
    212212        uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    … …  
    239239 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
    240240 *
    241  * @param page_and_ctx  A 64-bit value describing the fault. The most
    242  *                      significant 51 bits of the value contain the virtual
    243  *                      address which caused the fault truncated to the page
    244  *                      boundary. The least significant 13 bits of the value
    245  *                      contain the number of the context in which the fault
    246  *                      occurred.
     241 * @param tt            Trap type.
    247242 * @param istate        Interrupted state saved on the stack.
    248243 */
    249 void fast_data_access_mmu_miss(uint64_t page_and_ctx, istate_t *istate)
     244void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
    250245{
    251246        pte_t *t;
    252         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
    253         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
     247        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
     248        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
    254249        as_t *as = AS;
    255250
    … …  
    288283/** DTLB protection fault handler.
    289284 *
    290  * @param page_and_ctx  A 64-bit value describing the fault. The most
    291  *                      significant 51 bits of the value contain the virtual
    292  *                      address which caused the fault truncated to the page
    293  *                      boundary. The least significant 13 bits of the value
    294  *                      contain the number of the context in which the fault
    295  *                      occurred.
     285 * @param tt            Trap type.
    296286 * @param istate        Interrupted state saved on the stack.
    297287 */
    298 void fast_data_access_protection(uint64_t page_and_ctx, istate_t *istate)
     288void fast_data_access_protection(unsigned int tt, istate_t *istate)
    299289{
    300290        pte_t *t;
    301         uintptr_t va = DMISS_ADDRESS(page_and_ctx);
    302         uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
     291        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
     292        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
    303293        as_t *as = AS;
    304294

  • kernel/arch/sparc64/src/sun4v/sparc64.c

    raef669b rcade9c1  
    8484void arch_pre_mm_init(void)
    8585{
    86         if (config.cpu_active == 1)
     86        if (config.cpu_active == 1) {
    8787                trap_init();
     88                exc_arch_init();
     89        }
    8890}
    8991

  • kernel/arch/sparc64/src/trap/interrupt.c

    raef669b rcade9c1  
    6060            "instruction_access_error", false,
    6161            instruction_access_error);
     62
     63#ifdef SUN4V
     64        exc_register(TT_IAE_UNAUTH_ACCESS,
     65            "iae_unauth_access", false,
     66            instruction_access_exception);
     67        exc_register(TT_IAE_NFO_PAGE,
     68            "iae_nfo_page", false,
     69            instruction_access_exception);
     70#endif
     71
    6272        exc_register(TT_ILLEGAL_INSTRUCTION,
    6373            "illegal_instruction", false,
    … …  
    7282            "unimplemented_STD", false,
    7383            unimplemented_STD);
     84
     85#ifdef SUN4V
     86        exc_register(TT_DAE_INVALID_ASI,
     87            "dae_invalid_asi", false,
     88            data_access_exception);
     89        exc_register(TT_DAE_PRIVILEGE_VIOLATION,
     90            "dae_privilege_violation", false,
     91            data_access_exception);
     92        exc_register(TT_DAE_NC_PAGE,
     93            "dae_nc_page", false,
     94            data_access_exception);
     95        exc_register(TT_DAE_NC_PAGE,
     96            "dae_nc_page", false,
     97            data_access_exception);
     98        exc_register(TT_DAE_NFO_PAGE,
     99            "dae_nfo_page", false,
     100            data_access_exception);
     101#endif
     102
    74103        exc_register(TT_FP_DISABLED,
    75104            "fp_disabled", true,
    … …  
    116145            tick_interrupt);
    117146
    118 #ifdef SUN4u
     147#ifdef SUN4U
    119148        exc_register(TT_INTERRUPT_VECTOR_TRAP,
    120149            "interrupt_vector_trap", true,
    … …  
    131160            "fast_data_access_protection", true,
    132161            fast_data_access_protection);       
     162
     163#ifdef SUN4V
     164        exc_register(TT_CPU_MONDO,
     165            "cpu_mondo", true,
     166            cpu_mondo);
     167#endif
     168
    133169}
    134170

  • kernel/arch/sparc64/src/trap/sun4v/interrupt.c

    raef669b rcade9c1  
    9595 * register and processes the message (invokes a function call).
    9696 */
    97 void cpu_mondo(void)
     97void cpu_mondo(unsigned int tt, istate_t *istate)
    9898{
    9999#ifdef CONFIG_SMP

  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    raef669b rcade9c1  
    6666.global instruction_access_exception_tl0
    6767instruction_access_exception_tl0:
    68         PREEMPTIBLE_HANDLER instruction_access_exception
     68        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     69        clr %g5
     70        PREEMPTIBLE_HANDLER exc_dispatch
    6971
    7072/* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    … …  
    7779.global instruction_access_error_tl0
    7880instruction_access_error_tl0:
    79         PREEMPTIBLE_HANDLER instruction_access_error
     81        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     82        clr %g5
     83        PREEMPTIBLE_HANDLER exc_dispatch
    8084
    8185/* TT = 0x0b, TL = 0, IAE_unauth_access */
    … …  
    8387.global iae_unauth_access_tl0
    8488iae_unauth_access_tl0:
    85         PREEMPTIBLE_HANDLER instruction_access_exception
     89        mov TT_IAE_UNAUTH_ACCESS, %g2
     90        clr %g5
     91        PREEMPTIBLE_HANDLER exc_dispatch
    8692
    8793/* TT = 0x0c, TL = 0, IAE_nfo_page */
    … …  
    8995.global iae_nfo_page_tl0
    9096iae_nfo_page_tl0:
    91         PREEMPTIBLE_HANDLER instruction_access_exception
     97        mov TT_IAE_NFO_PAGE, %g2
     98        clr %g5
     99        PREEMPTIBLE_HANDLER exc_dispatch
    92100
    93101/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    95103.global illegal_instruction_tl0
    96104illegal_instruction_tl0:
    97         PREEMPTIBLE_HANDLER illegal_instruction
     105        mov TT_ILLEGAL_INSTRUCTION, %g2
     106        clr %g5
     107        PREEMPTIBLE_HANDLER exc_dispatch
    98108
    99109/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    101111.global privileged_opcode_tl0
    102112privileged_opcode_tl0:
    103         PREEMPTIBLE_HANDLER privileged_opcode
     113        mov TT_PRIVILEGED_OPCODE, %g2
     114        clr %g5
     115        PREEMPTIBLE_HANDLER exc_dispatch
    104116
    105117/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    107119.global unimplemented_LDD_tl0
    108120unimplemented_LDD_tl0:
    109         PREEMPTIBLE_HANDLER unimplemented_LDD
     121        mov TT_UNIMPLEMENTED_LDD, %g2
     122        clr %g5
     123        PREEMPTIBLE_HANDLER exc_dispatch
    110124
    111125/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    113127.global unimplemented_STD_tl0
    114128unimplemented_STD_tl0:
    115         PREEMPTIBLE_HANDLER unimplemented_STD
     129        mov TT_UNIMPLEMENTED_STD, %g2
     130        clr %g5
     131        PREEMPTIBLE_HANDLER exc_dispatch
    116132
    117133/* TT = 0x14, TL = 0, DAE_invalid_asi */
    … …  
    119135.global dae_invalid_asi_tl0
    120136dae_invalid_asi_tl0:
    121         PREEMPTIBLE_HANDLER data_access_exception
     137        mov TT_DAE_INVALID_ASI, %g2
     138        clr %g5
     139        PREEMPTIBLE_HANDLER exc_dispatch
    122140
    123141/* TT = 0x15, TL = 0, DAE_privilege_violation */
    … …  
    125143.global dae_privilege_violation_tl0
    126144dae_privilege_violation_tl0:
    127         PREEMPTIBLE_HANDLER data_access_exception
     145        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
     146        clr %g5
     147        PREEMPTIBLE_HANDLER exc_dispatch
    128148
    129149/* TT = 0x16, TL = 0, DAE_nc_page */
    … …  
    131151.global dae_nc_page_tl0
    132152dae_nc_page_tl0:
    133         PREEMPTIBLE_HANDLER data_access_exception
     153        mov TT_DAE_NC_PAGE, %g2
     154        clr %g5
     155        PREEMPTIBLE_HANDLER exc_dispatch
    134156
    135157/* TT = 0x17, TL = 0, DAE_nfo_page */
    … …  
    137159.global dae_nfo_page_tl0
    138160dae_nfo_page_tl0:
    139         PREEMPTIBLE_HANDLER data_access_exception
     161        mov TT_DAE_NFO_PAGE, %g2
     162        clr %g5
     163        PREEMPTIBLE_HANDLER exc_dispatch
    140164
    141165/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    143167.global fb_disabled_tl0
    144168fp_disabled_tl0:
    145         PREEMPTIBLE_HANDLER fp_disabled
     169        mov TT_FP_DISABLED, %g2
     170        clr %g5
     171        PREEMPTIBLE_HANDLER exc_dispatch
    146172
    147173/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    149175.global fb_exception_ieee_754_tl0
    150176fp_exception_ieee_754_tl0:
    151         PREEMPTIBLE_HANDLER fp_exception_ieee_754
     177        mov TT_FP_EXCEPTION_IEEE_754, %g2
     178        clr %g5
     179        PREEMPTIBLE_HANDLER exc_dispatch
    152180
    153181/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    155183.global fb_exception_other_tl0
    156184fp_exception_other_tl0:
    157         PREEMPTIBLE_HANDLER fp_exception_other
     185        mov TT_FP_EXCEPTION_OTHER, %g2
     186        clr %g5
     187        PREEMPTIBLE_HANDLER exc_dispatch
    158188
    159189/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    161191.global tag_overflow_tl0
    162192tag_overflow_tl0:
    163         PREEMPTIBLE_HANDLER tag_overflow
     193        mov TT_TAG_OVERFLOW, %g2
     194        clr %g5
     195        PREEMPTIBLE_HANDLER exc_dispatch
    164196
    165197/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    173205.global division_by_zero_tl0
    174206division_by_zero_tl0:
    175         PREEMPTIBLE_HANDLER division_by_zero
     207        mov TT_DIVISION_BY_ZERO, %g2
     208        clr %g5
     209        PREEMPTIBLE_HANDLER exc_dispatch
    176210
    177211/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    180214.global data_access_exception_tl0
    181215data_access_exception_tl0:
    182         PREEMPTIBLE_HANDLER data_access_exception
     216        mov TT_DATA_ACCESS_EXCEPTION, %g2
     217        clr %g5
     218        PREEMPTIBLE_HANDLER exc_dispatch
    183219
    184220/* TT = 0x31, TL = 0, data_access_mmu_miss */
    … …  
    192228.global data_access_error_tl0
    193229data_access_error_tl0:
    194         PREEMPTIBLE_HANDLER data_access_error
     230        mov TT_DATA_ACCESS_ERROR, %g2
     231        clr %g5
     232        PREEMPTIBLE_HANDLER exc_dispatch
    195233
    196234/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    198236.global mem_address_not_aligned_tl0
    199237mem_address_not_aligned_tl0:
    200         PREEMPTIBLE_HANDLER mem_address_not_aligned
     238        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     239        clr %g5
     240        PREEMPTIBLE_HANDLER exc_dispatch
    201241
    202242/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    204244.global LDDF_mem_address_not_aligned_tl0
    205245LDDF_mem_address_not_aligned_tl0:
    206         PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
     246        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     247        clr %g5
     248        PREEMPTIBLE_HANDLER exc_dispatch
    207249
    208250/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    210252.global STDF_mem_address_not_aligned_tl0
    211253STDF_mem_address_not_aligned_tl0:
    212         PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
     254        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     255        clr %g5
     256        PREEMPTIBLE_HANDLER exc_dispatch
    213257
    214258/* TT = 0x37, TL = 0, privileged_action */
    … …  
    216260.global privileged_action_tl0
    217261privileged_action_tl0:
    218         PREEMPTIBLE_HANDLER privileged_action
     262        mov TT_PRIVILEGED_ACTION, %g2
     263        clr %g5
     264        PREEMPTIBLE_HANDLER exc_dispatch
    219265
    220266/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    222268.global LDQF_mem_address_not_aligned_tl0
    223269LDQF_mem_address_not_aligned_tl0:
    224         PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
     270        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     271        clr %g5
     272        PREEMPTIBLE_HANDLER exc_dispatch
    225273
    226274/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    228276.global STQF_mem_address_not_aligned_tl0
    229277STQF_mem_address_not_aligned_tl0:
    230         PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
     278        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     279        clr %g5
     280        PREEMPTIBLE_HANDLER exc_dispatch
    231281
    232282/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    234284.global interrupt_level_1_handler_tl0
    235285interrupt_level_1_handler_tl0:
    236         INTERRUPT_LEVEL_N_HANDLER 1
     286        mov TT_INTERRUPT_LEVEL_1, %g2
     287        clr %g5
     288        PREEMPTIBLE_HANDLER exc_dispatch
    237289
    238290/* TT = 0x42, TL = 0, interrupt_level_2 handler */
    … …  
    240292.global interrupt_level_2_handler_tl0
    241293interrupt_level_2_handler_tl0:
    242         INTERRUPT_LEVEL_N_HANDLER 2
     294        mov TT_INTERRUPT_LEVEL_2, %g2
     295        clr %g5
     296        PREEMPTIBLE_HANDLER exc_dispatch
    243297
    244298/* TT = 0x43, TL = 0, interrupt_level_3 handler */
    … …  
    246300.global interrupt_level_3_handler_tl0
    247301interrupt_level_3_handler_tl0:
    248         INTERRUPT_LEVEL_N_HANDLER 3
     302        mov TT_INTERRUPT_LEVEL_3, %g2
     303        clr %g5
     304        PREEMPTIBLE_HANDLER exc_dispatch
    249305
    250306/* TT = 0x44, TL = 0, interrupt_level_4 handler */
    … …  
    252308.global interrupt_level_4_handler_tl0
    253309interrupt_level_4_handler_tl0:
    254         INTERRUPT_LEVEL_N_HANDLER 4
     310        mov TT_INTERRUPT_LEVEL_4, %g2
     311        clr %g5
     312        PREEMPTIBLE_HANDLER exc_dispatch
    255313
    256314/* TT = 0x45, TL = 0, interrupt_level_5 handler */
    … …  
    258316.global interrupt_level_5_handler_tl0
    259317interrupt_level_5_handler_tl0:
    260         INTERRUPT_LEVEL_N_HANDLER 5
     318        mov TT_INTERRUPT_LEVEL_5, %g2
     319        clr %g5
     320        PREEMPTIBLE_HANDLER exc_dispatch
    261321
    262322/* TT = 0x46, TL = 0, interrupt_level_6 handler */
    … …  
    264324.global interrupt_level_6_handler_tl0
    265325interrupt_level_6_handler_tl0:
    266         INTERRUPT_LEVEL_N_HANDLER 6
     326        mov TT_INTERRUPT_LEVEL_6, %g2
     327        clr %g5
     328        PREEMPTIBLE_HANDLER exc_dispatch
    267329
    268330/* TT = 0x47, TL = 0, interrupt_level_7 handler */
    … …  
    270332.global interrupt_level_7_handler_tl0
    271333interrupt_level_7_handler_tl0:
    272         INTERRUPT_LEVEL_N_HANDLER 7
     334        mov TT_INTERRUPT_LEVEL_7, %g2
     335        clr %g5
     336        PREEMPTIBLE_HANDLER exc_dispatch
    273337
    274338/* TT = 0x48, TL = 0, interrupt_level_8 handler */
    … …  
    276340.global interrupt_level_8_handler_tl0
    277341interrupt_level_8_handler_tl0:
    278         INTERRUPT_LEVEL_N_HANDLER 8
     342        mov TT_INTERRUPT_LEVEL_8, %g2
     343        clr %g5
     344        PREEMPTIBLE_HANDLER exc_dispatch
    279345
    280346/* TT = 0x49, TL = 0, interrupt_level_9 handler */
    … …  
    282348.global interrupt_level_9_handler_tl0
    283349interrupt_level_9_handler_tl0:
    284         INTERRUPT_LEVEL_N_HANDLER 9
     350        mov TT_INTERRUPT_LEVEL_9, %g2
     351        clr %g5
     352        PREEMPTIBLE_HANDLER exc_dispatch
    285353
    286354/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
    … …  
    288356.global interrupt_level_10_handler_tl0
    289357interrupt_level_10_handler_tl0:
    290         INTERRUPT_LEVEL_N_HANDLER 10
     358        mov TT_INTERRUPT_LEVEL_10, %g2
     359        clr %g5
     360        PREEMPTIBLE_HANDLER exc_dispatch
    291361
    292362/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
    … …  
    294364.global interrupt_level_11_handler_tl0
    295365interrupt_level_11_handler_tl0:
    296         INTERRUPT_LEVEL_N_HANDLER 11
     366        mov TT_INTERRUPT_LEVEL_11, %g2
     367        clr %g5
     368        PREEMPTIBLE_HANDLER exc_dispatch
    297369
    298370/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
    … …  
    300372.global interrupt_level_12_handler_tl0
    301373interrupt_level_12_handler_tl0:
    302         INTERRUPT_LEVEL_N_HANDLER 12
     374        mov TT_INTERRUPT_LEVEL_12, %g2
     375        clr %g5
     376        PREEMPTIBLE_HANDLER exc_dispatch
    303377
    304378/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
    … …  
    306380.global interrupt_level_13_handler_tl0
    307381interrupt_level_13_handler_tl0:
    308         INTERRUPT_LEVEL_N_HANDLER 13
     382        mov TT_INTERRUPT_LEVEL_13, %g2
     383        clr %g5
     384        PREEMPTIBLE_HANDLER exc_dispatch
    309385
    310386/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
    … …  
    312388.global interrupt_level_14_handler_tl0
    313389interrupt_level_14_handler_tl0:
    314         INTERRUPT_LEVEL_N_HANDLER 14
     390        mov TT_INTERRUPT_LEVEL_14, %g2
     391        clr %g5
     392        PREEMPTIBLE_HANDLER exc_dispatch
    315393
    316394/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
    … …  
    318396.global interrupt_level_15_handler_tl0
    319397interrupt_level_15_handler_tl0:
    320         INTERRUPT_LEVEL_N_HANDLER 15
     398        mov TT_INTERRUPT_LEVEL_15, %g2
     399        clr %g5
     400        PREEMPTIBLE_HANDLER exc_dispatch
    321401
    322402/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    … …  
    342422.global cpu_mondo_handler_tl0
    343423cpu_mondo_handler_tl0:
    344 PREEMPTIBLE_HANDLER cpu_mondo
     424        mov TT_CPU_MONDO, %g2
     425        clr %g5
     426        PREEMPTIBLE_HANDLER cpu_mondo
    345427
    346428/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    392474.global trap_instruction_\cur\()_tl0
    393475trap_instruction_\cur\()_tl0:
     476        mov \cur, %g2
    394477        ba %xcc, trap_instruction_handler
    395         mov \cur, %g2
     478        clr %g5
    396479.endr
    397480
    … …  
    406489instruction_access_exception_tl1:
    407490        wrpr %g0, 1, %tl
    408         PREEMPTIBLE_HANDLER instruction_access_exception
     491        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     492        clr %g5
     493        PREEMPTIBLE_HANDLER exc_dispatch
    409494
    410495/* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    … …  
    419504instruction_access_error_tl1:
    420505        wrpr %g0, 1, %tl
    421         PREEMPTIBLE_HANDLER instruction_access_error
     506        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     507        clr %g5
     508        PREEMPTIBLE_HANDLER exc_dispatch
    422509
    423510/* TT = 0x0b, TL > 0, IAE_unauth_access */
    … …  
    426513iae_unauth_access_tl1:
    427514        wrpr %g0, 1, %tl
    428         PREEMPTIBLE_HANDLER instruction_access_exception
     515        mov TT_IAE_UNAUTH_ACCESS, %g2
     516        clr %g5
     517        PREEMPTIBLE_HANDLER exc_dispatch
    429518
    430519/* TT = 0x0c, TL > 0, IAE_nfo_page */
    … …  
    433522iae_nfo_page_tl1:
    434523        wrpr %g0, 1, %tl
    435         PREEMPTIBLE_HANDLER instruction_access_exception
     524        mov TT_IAE_NFO_PAGE, %g2
     525        clr %g5
     526        PREEMPTIBLE_HANDLER exc_dispatch
    436527
    437528/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    440531illegal_instruction_tl1:
    441532        wrpr %g0, 1, %tl
    442         PREEMPTIBLE_HANDLER illegal_instruction
     533        mov TT_ILLEGAL_INSTRUCTION, %g2
     534        clr %g5
     535        PREEMPTIBLE_HANDLER exc_dispatch
    443536
    444537/* TT = 0x14, TL > 0, DAE_invalid_asi */
    … …  
    447540dae_invalid_asi_tl1:
    448541        wrpr %g0, 1, %tl
    449         PREEMPTIBLE_HANDLER data_access_exception
     542        mov TT_DAE_INVALID_ASI, %g2
     543        clr %g5
     544        PREEMPTIBLE_HANDLER exc_dispatch
    450545
    451546/* TT = 0x15, TL > 0, DAE_privilege_violation */
    … …  
    454549dae_privilege_violation_tl1:
    455550        wrpr %g0, 1, %tl
    456         PREEMPTIBLE_HANDLER data_access_exception
     551        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
     552        clr %g5
     553        PREEMPTIBLE_HANDLER exc_dispatch
    457554
    458555/* TT = 0x16, TL > 0, DAE_nc_page */
    … …  
    461558dae_nc_page_tl1:
    462559        wrpr %g0, 1, %tl
    463         PREEMPTIBLE_HANDLER data_access_exception
     560        mov TT_DAE_NC_PAGE, %g2
     561        clr %g5
     562        PREEMPTIBLE_HANDLER exc_dispatch
    464563
    465564/* TT = 0x17, TL > 0, DAE_nfo_page */
    … …  
    468567dae_nfo_page_tl1:
    469568        wrpr %g0, 1, %tl
    470         PREEMPTIBLE_HANDLER data_access_exception
     569        mov TT_DAE_NFO_PAGE, %g2
     570        clr %g5
     571        PREEMPTIBLE_HANDLER exc_dispatch
    471572
    472573/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    481582division_by_zero_tl1:
    482583        wrpr %g0, 1, %tl
    483         PREEMPTIBLE_HANDLER division_by_zero
     584        mov TT_DIVISION_BY_ZERO, %g2
     585        clr %g5
     586        PREEMPTIBLE_HANDLER exc_dispatch
    484587
    485588/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    487590.global data_access_exception_tl1
    488591data_access_exception_tl1:
    489         /*wrpr %g0, 1, %tl
    490         wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    491         PREEMPTIBLE_HANDLER data_access_exception*/
     592        wrpr %g0, 1, %tl
     593        mov TT_DATA_ACCESS_EXCEPTION, %g2
     594        clr %g5
     595        PREEMPTIBLE_HANDLER exc_dispatch
    492596
    493597/* TT = 0x31, TL > 0, data_access_mmu_miss */
    … …  
    502606data_access_error_tl1:
    503607        wrpr %g0, 1, %tl
    504         PREEMPTIBLE_HANDLER data_access_error
     608        mov TT_DATA_ACCESS_ERROR, %g2
     609        clr %g5
     610        PREEMPTIBLE_HANDLER exc_dispatch
    505611
    506612/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    509615mem_address_not_aligned_tl1:
    510616        wrpr %g0, 1, %tl
    511         PREEMPTIBLE_HANDLER mem_address_not_aligned
     617        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     618        clr %g5
     619        PREEMPTIBLE_HANDLER exc_dispatch
    512620
    513621/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    528636cpu_mondo_handler_tl1:
    529637        wrpr %g0, %tl
    530         PREEMPTIBLE_HANDLER cpu_mondo
     638        mov TT_CPU_MONDO, %g2
     639        clr %g5
     640        PREEMPTIBLE_HANDLER exc_dispatch
    531641
    532642/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    654764.else
    655765        ! store the syscall number on the stack as 7th argument
    656         stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6]
     766        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    657767.endif
    658768
    … …  
    664774        rdpr %tnpc, %g3
    665775
    666         stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
    667         stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
    668         stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     776        stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
     777        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
     778        stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
    669779
    670780        /*
    671781         * Save the Y register.
    672          * This register is deprecated according to SPARC V9 specification
    673          * and is only present for backward compatibility with previous
    674          * versions of the SPARC architecture.
    675          * Surprisingly, gcc makes use of this register without a notice.
    676782         */
    677783        rd %y, %g4
    678         stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     784        stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
     785
     786        /*
     787         * Save the faulting page and context.
     788         */
     789        stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
    679790
    680791        /* switch to TL = 0, explicitly enable FPU */
    … …  
    689800        /* call higher-level service routine, pass istate as its 2nd parameter */
    690801        call %l0
    691         add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     802        add %sp, STACK_BIAS, %o1
    692803.else
    693804        /* Call the higher-level syscall handler. */
    … …  
    711822
    712823        /* Read TSTATE, TPC and TNPC from saved copy. */
    713         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
    714         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
    715         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     824        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
     825        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
     826        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
    716827
    717828        /* Copy PSTATE.PEF to the in-register copy of TSTATE. */
    … …  
    728839
    729840        /* Restore Y. */
    730         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     841        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
    731842        wr %g4, %y
    732843       
    … …  
    750861         */
    751862        mov %sp, %g2
    752         stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
    753         stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
    754         stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
    755         stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
    756         stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
    757         stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
    758         stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
    759         stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     863        stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
     864        stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
     865        stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
     866        stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
     867        stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
     868        stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
     869        stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
     870        stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
    760871        wrpr %l0, 0, %cwp
    761872        mov %g2, %sp
    762         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
    763         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
    764         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
    765         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
    766         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
    767         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
    768         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
    769         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     873        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
     874        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
     875        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
     876        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
     877        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
     878        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
     879        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
     880        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
    770881.endm
    771882
    … …  
    774885 */
    775886.macro PREEMPTIBLE_HANDLER_KERNEL
    776 
    777         /*
    778          * ASSERT(%tl == 1)
    779          */
    780         rdpr %tl, %g3
    781         cmp %g3, 1
    782         be %xcc, 1f
    783         nop
    784 
    785         ! this is for debugging, if we ever get here it will be easy to find
    786 0:      ba,a %xcc, 0b
    787 
    788 1:
    789887        /* prevent unnecessary CLEANWIN exceptions */
    790888        wrpr %g0, NWINDOWS - 1, %cleanwin
    … …  
    8039012:
    804902        /* ask for new register window */
    805         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     903        save %sp, -ISTATE_SIZE, %sp
    806904
    807905        MIDDLE_PART 0
    … …  
    882980        set SCRATCHPAD_KSTACK, %g4
    883981        ldxa [%g4] ASI_SCRATCHPAD, %g6
    884         save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     982        save %g6, -ISTATE_SIZE, %sp
    885983
    886984.if \is_syscall
    … …  
    10151113         * If the:
    10161114         *
    1017          *      save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     1115         *      save %g6, -ISTATE_SIZE, %sp
    10181116         *
    10191117         * instruction trapped and spilled a register window into the userspace
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