Changeset b9b103d3 in mainline for arch

Timestamp:

2005-10-27T15:53:40Z (20 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

39cb79a

Parents:

807d2d4

Message:

Enable/disable CPU memory barriers at compile time

Location:

arch/ia32

Files:

• Makefile.inc (modified) (1 diff)
• include/barrier.h (modified) (2 diffs)

arch/ia32/Makefile.inc

@@ -23 +23 @@
 DEFS:=-DARCH=$(ARCH) -DFPU_LAZY
 
+ifeq (${STRONG_ORDERING},yes)
+        DEFS+=-D__STRONG_ORDERING__
+endif
+
 ifdef SMP
-DEFS+=-D$(SMP)
+        DEFS+=-D$(SMP)
 endif
 
 ifdef HT
-DEFS+=-D$(HT)
+        DEFS+=-D$(HT)
 endif
 

arch/ia32/include/barrier.h

@@ -44 +44 @@
 #define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
 
+#ifdef __STRONG_ORDERING__
+
+#define memory_barrier()
+#define read_barrier()
+#define write_barrier()
+
+#else
+
 #define memory_barrier()        __asm__ volatile ("mfence\n" ::: "memory")
 #define read_barrier()          __asm__ volatile ("sfence\n" ::: "memory")
@@ -49 +57 @@
 
 #endif
+
+#endif