Changeset b97b348 in mainline for kernel/arch/sparc64/src
- Timestamp:
- 2010-05-12T20:00:19Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- be6cef1b
- Parents:
- f09d891
- Location:
- kernel/arch/sparc64/src
- Files:
-
- 1 deleted
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/smp/sun4v/smp.c
rf09d891 rb97b348 433 433 if (__hypercall_fast4(CPU_START, cpuid, 434 434 (uint64_t) KA2PA(kernel_image_start), KA2PA(trap_table), 435 physmem_ start) != EOK)435 physmem_base) != EOK) 436 436 return false; 437 437 #endif -
kernel/arch/sparc64/src/sun4u/start.S
rf09d891 rb97b348 36 36 #include <arch/mm/tlb.h> 37 37 #include <arch/mm/tte.h> 38 #include <arch/mm/cache_spec.h> 38 39 39 40 #ifdef CONFIG_SMP … … 62 63 * 63 64 * The registers are expected to be in this state: 64 * - %o0 bootinfo structure address (BSP only) 65 * - %o1 starting address of physical memory 65 * - %o0 starting address of physical memory 66 66 * + bootstrap processor flag 67 67 * bits 63...1: physical memory starting address / 2 68 68 * bit 0: non-zero on BSP processor, zero on AP processors 69 * - %o1 bootinfo structure address (BSP only) 70 * 69 71 * 70 72 * Moreover, we depend on boot having established the following environment: … … 77 79 kernel_image_start: 78 80 mov BSP_FLAG, %l0 79 and %o 1, %l0, %l7 ! l7 <= bootstrap processor?80 andn %o 1, %l0, %l6 ! l6 <= start of physical memory81 and %o0, %l0, %l7 ! l7 <= bootstrap processor? 82 andn %o0, %l0, %l6 ! l6 <= start of physical memory 81 83 82 84 ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. … … 268 270 or %l3, %l5, %l3 269 271 stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] 270 271 /* 272 * Flush D-Cache. 273 */ 274 call dcache_flush 275 nop 276 272 273 ! flush the whole D-cache 274 set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1 275 stxa %g0, [%g1] ASI_DCACHE_TAG 276 277 0: 278 membar #Sync 279 subcc %g1, DCACHE_LINE_SIZE, %g1 280 bnz,pt %xcc, 0b 281 282 stxa %g0, [%g1] ASI_DCACHE_TAG 283 membar #Sync 284 277 285 /* 278 286 * So far, we have not touched the stack. … … 282 290 or %sp, %lo(temporary_boot_stack), %sp 283 291 sub %sp, STACK_BIAS, %sp 284 292 293 /* 294 * Call arch_pre_main(bootinfo) 295 */ 296 mov %o1, %o0 285 297 call arch_pre_main 286 298 nop -
kernel/arch/sparc64/src/sun4v/start.S
rf09d891 rb97b348 93 93 * 94 94 * The registers are expected to be in this state: 95 * - %o0 bootinfo structure address (BSP only) 96 * - %o1 starting address of physical memory 95 * - %o0 starting address of physical memory 97 96 * + bootstrap processor flag 98 97 * bits 63...1: physical memory starting address / 2 99 98 * bit 0: non-zero on BSP processor, zero on AP processors 99 * - %o1 bootinfo structure address (BSP only) 100 * 100 101 * 101 102 * Moreover, we depend on boot having established the following environment: … … 107 108 kernel_image_start: 108 109 mov BSP_FLAG, %l0 109 and %o 1, %l0, %l7 ! l7 <= bootstrap processor?110 andn %o 1, %l0, %l6 ! l6 <= start of physical memory111 or %o 0, %g0, %l0110 and %o0, %l0, %l7 ! l7 <= bootstrap processor? 111 andn %o0, %l0, %l6 ! l6 <= start of physical memory 112 or %o1, %g0, %l1 112 113 113 114 ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. … … 246 247 sub %sp, STACK_BIAS, %sp 247 248 248 or %l0, %g0, %o0 249 /* 250 * Call arch_pre_main(bootinfo) 251 */ 252 or %l1, %g0, %o0 249 253 call arch_pre_main 250 254 nop
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