Changeset b97b348 in mainline for kernel/arch/sparc64

Timestamp:

2010-05-12T20:00:19Z (15 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

be6cef1b

Parents:

f09d891

Message:

do not use ofw_quiesce() (it can actually make more harm than good)
fix the order of arguments passed from the bootloader to kernel on sparc64 (this fixes booting on machines with non-zero physical address start)
remove separate cache.S, use the code directly in start.S

Location:

kernel/arch/sparc64

Files:

• Makefile.inc (modified) (1 diff)
• include/boot/boot.h (modified) (1 diff)
• include/mm/cache_spec.h (modified) (2 diffs)
• src/mm/cache.S (deleted)
• src/smp/sun4v/smp.c (modified) (1 diff)
• src/sun4u/start.S (modified) (5 diffs)
• src/sun4v/start.S (modified) (3 diffs)

kernel/arch/sparc64/Makefile.inc

@@ -90 +90 @@
         arch/$(KARCH)/src/trap/$(USARCH)/interrupt.c
 
-ifeq ($(USARCH),sun4u)
-        ARCH_SOURCES += \
-                arch/$(KARCH)/src/mm/cache.S
-endif
-
 ifeq ($(USARCH),sun4v)
         ARCH_SOURCES += \

kernel/arch/sparc64/include/boot/boot.h

@@ -87 +87 @@
 
 extern memmap_t memmap;
-extern uintptr_t physmem_start;
 
 #endif

kernel/arch/sparc64/include/mm/cache_spec.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64mm       
+/** @addtogroup sparc64mm
  * @{
  */
@@ -39 +39 @@
  * The following macros are valid for the following processors:
  *
- *      UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
- *      UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
- * 
+ *  UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
+ *  UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
+ *
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
- 
+
 #if defined (US)
-#define DCACHE_SIZE             (16 * 1024)
+        #define DCACHE_SIZE  (16 * 1024)
 #elif defined (US3)
-#define DCACHE_SIZE             (64 * 1024)
+        #define DCACHE_SIZE  (64 * 1024)
 #endif
-#define DCACHE_LINE_SIZE        32      
+
+#define DCACHE_LINE_SIZE  32
+#define DCACHE_TAG_SHIFT  2
 
 #endif

kernel/arch/sparc64/src/smp/sun4v/smp.c

@@ -433 +433 @@
         if (__hypercall_fast4(CPU_START, cpuid,
             (uint64_t) KA2PA(kernel_image_start), KA2PA(trap_table),
-            physmem_start) != EOK)
+            physmem_base) != EOK)
                 return false;
 #endif

kernel/arch/sparc64/src/sun4u/start.S

@@ -36 +36 @@
 #include <arch/mm/tlb.h>
 #include <arch/mm/tte.h>
+#include <arch/mm/cache_spec.h>
 
 #ifdef CONFIG_SMP
@@ -62 +63 @@
  *
  * The registers are expected to be in this state:
- *  - %o0 bootinfo structure address (BSP only)
- *  - %o1 starting address of physical memory
+ *  - %o0 starting address of physical memory
  *        + bootstrap processor flag
  *          bits 63...1: physical memory starting address / 2
  *          bit 0:       non-zero on BSP processor, zero on AP processors
+ *  - %o1 bootinfo structure address (BSP only)
+ *
  *
  * Moreover, we depend on boot having established the following environment:
@@ -77 +79 @@
 kernel_image_start:
         mov BSP_FLAG, %l0
-        and %o1, %l0, %l7                       ! l7 <= bootstrap processor?
-        andn %o1, %l0, %l6                      ! l6 <= start of physical memory
+        and %o0, %l0, %l7                       ! l7 <= bootstrap processor?
+        andn %o0, %l0, %l6                      ! l6 <= start of physical memory
 
         ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
@@ -268 +270 @@
         or %l3, %l5, %l3
         stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
-
-        /*
-         * Flush D-Cache.
-         */
-        call dcache_flush
-        nop
-
+        
+        ! flush the whole D-cache
+        set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1
+        stxa %g0, [%g1] ASI_DCACHE_TAG
+        
+0:
+        membar #Sync
+        subcc %g1, DCACHE_LINE_SIZE, %g1
+        bnz,pt %xcc, 0b
+        
+        stxa %g0, [%g1] ASI_DCACHE_TAG
+        membar #Sync
+        
         /*
          * So far, we have not touched the stack.
@@ -282 +290 @@
         or %sp, %lo(temporary_boot_stack), %sp
         sub %sp, STACK_BIAS, %sp
-
+        
+        /*
+         * Call arch_pre_main(bootinfo)
+         */
+        mov %o1, %o0
         call arch_pre_main
         nop

kernel/arch/sparc64/src/sun4v/start.S

@@ -93 +93 @@
  *
  * The registers are expected to be in this state:
- *  - %o0 bootinfo structure address (BSP only)
- *  - %o1 starting address of physical memory
+ *  - %o0 starting address of physical memory
  *        + bootstrap processor flag
  *          bits 63...1: physical memory starting address / 2
  *          bit 0:       non-zero on BSP processor, zero on AP processors
+ *  - %o1 bootinfo structure address (BSP only)
+ *
  *
  * Moreover, we depend on boot having established the following environment:
@@ -107 +108 @@
 kernel_image_start:
         mov BSP_FLAG, %l0
-        and %o1, %l0, %l7                       ! l7 <= bootstrap processor?
-        andn %o1, %l0, %l6                      ! l6 <= start of physical memory
-        or %o0, %g0, %l0
+        and %o0, %l0, %l7                       ! l7 <= bootstrap processor?
+        andn %o0, %l0, %l6                      ! l6 <= start of physical memory
+        or %o1, %g0, %l1
 
         ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
@@ -246 +247 @@
         sub %sp, STACK_BIAS, %sp
 
-        or %l0, %g0, %o0
+        /*
+         * Call arch_pre_main(bootinfo)
+         */
+        or %l1, %g0, %o0
         call arch_pre_main
         nop