Changeset b3e8c90 in mainline for kernel/arch/sparc64/include/barrier.h

Timestamp:

2006-08-01T11:24:27Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e386cbf

Parents:

c049309

Message:

sparc64 work.

1. Formatting fixes.
2. When writing to DMMU ASI's, simple membar() can be used in place of flush().
3. Substantial changes in the way the TLB is taken over.
4. Remove unneeded functions.

This is the first revision that also runs on a real world Ultra 5 with UltraSPARC IIi
processor.

Note that 3. needs further work as the current implementation depends on the fact
that the compiler will use registers for local variables in take_over_tlb_and_tt().
Rewrite of that function into assembly is to follow.

File:

• kernel/arch/sparc64/include/barrier.h (modified) (1 diff)

kernel/arch/sparc64/include/barrier.h

@@ -55 +55 @@
          */
          
-        /*
-         * %i7 should provide address that is always mapped in DTLB
-         * as it is a pointer to kernel code.
-         */
-        __asm__ volatile ("flush %i7\n");
+        __asm__ volatile ("flush %0\n" :: "r" (0x400000));
 }