Changeset b1c57a8 in mainline for kernel/arch/amd64

Timestamp:

2014-10-09T15:03:55Z (11 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e367939c

Parents:

21799398 (diff), 207e8880 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge from lp:~adam-hraska+lp/helenos/rcu/.

Only merge from the feature branch and resolve all conflicts.

Location:

kernel/arch/amd64

Files:

• Makefile.inc (modified) (1 diff)
• include/arch/atomic.h (modified) (2 diffs)
• include/arch/cpu.h (modified) (1 diff)
• include/arch/interrupt.h (modified) (1 diff)
• src/amd64.c (modified) (1 diff)
• src/cpu/cpu.c (modified) (1 diff)
• src/interrupt.c (modified) (3 diffs)
• src/smp/smp_call.c (added)

kernel/arch/amd64/Makefile.inc

@@ -84 +84 @@
                 arch/$(KARCH)/src/smp/ipi.c \
                 arch/$(KARCH)/src/smp/mps.c \
+                arch/$(KARCH)/src/smp/smp_call.c \
                 arch/$(KARCH)/src/smp/smp.c
 endif

kernel/arch/amd64/include/arch/atomic.h

@@ -1 +1 @@
 /*
  * Copyright (c) 2001-2004 Jakub Jermar
+ * Copyright (c) 2012      Adam Hraska
  * All rights reserved.
  *
@@ -140 +141 @@
 }
 
+
+#define _atomic_cas_impl(pptr, exp_val, new_val, old_val, prefix) \
+({ \
+        switch (sizeof(typeof(*(pptr)))) { \
+        case 1: \
+                asm volatile ( \
+                        prefix " cmpxchgb %[newval], %[ptr]\n" \
+                        : /* Output operands. */ \
+                        /* Old/current value is returned in eax. */ \
+                        [oldval] "=a" (old_val), \
+                        /* (*ptr) will be read and written to, hence "+" */ \
+                        [ptr] "+m" (*pptr) \
+                        : /* Input operands. */ \
+                        /* Expected value must be in eax. */ \
+                        [expval] "a" (exp_val), \
+                        /* The new value may be in any register. */ \
+                        [newval] "r" (new_val) \
+                        : "memory" \
+                ); \
+                break; \
+        case 2: \
+                asm volatile ( \
+                        prefix " cmpxchgw %[newval], %[ptr]\n" \
+                        : /* Output operands. */ \
+                        /* Old/current value is returned in eax. */ \
+                        [oldval] "=a" (old_val), \
+                        /* (*ptr) will be read and written to, hence "+" */ \
+                        [ptr] "+m" (*pptr) \
+                        : /* Input operands. */ \
+                        /* Expected value must be in eax. */ \
+                        [expval] "a" (exp_val), \
+                        /* The new value may be in any register. */ \
+                        [newval] "r" (new_val) \
+                        : "memory" \
+                ); \
+                break; \
+        case 4: \
+                asm volatile ( \
+                        prefix " cmpxchgl %[newval], %[ptr]\n" \
+                        : /* Output operands. */ \
+                        /* Old/current value is returned in eax. */ \
+                        [oldval] "=a" (old_val), \
+                        /* (*ptr) will be read and written to, hence "+" */ \
+                        [ptr] "+m" (*pptr) \
+                        : /* Input operands. */ \
+                        /* Expected value must be in eax. */ \
+                        [expval] "a" (exp_val), \
+                        /* The new value may be in any register. */ \
+                        [newval] "r" (new_val) \
+                        : "memory" \
+                ); \
+                break; \
+        case 8: \
+                asm volatile ( \
+                        prefix " cmpxchgq %[newval], %[ptr]\n" \
+                        : /* Output operands. */ \
+                        /* Old/current value is returned in eax. */ \
+                        [oldval] "=a" (old_val), \
+                        /* (*ptr) will be read and written to, hence "+" */ \
+                        [ptr] "+m" (*pptr) \
+                        : /* Input operands. */ \
+                        /* Expected value must be in eax. */ \
+                        [expval] "a" (exp_val), \
+                        /* The new value may be in any register. */ \
+                        [newval] "r" (new_val) \
+                        : "memory" \
+                ); \
+                break; \
+        } \
+})
+
+
+#ifndef local_atomic_cas
+
+#define local_atomic_cas(pptr, exp_val, new_val) \
+({ \
+        /* Use proper types and avoid name clashes */ \
+        typeof(*(pptr)) _old_val_cas; \
+        typeof(*(pptr)) _exp_val_cas = exp_val; \
+        typeof(*(pptr)) _new_val_cas = new_val; \
+        _atomic_cas_impl(pptr, _exp_val_cas, _new_val_cas, _old_val_cas, ""); \
+        \
+        _old_val_cas; \
+})
+
+#else
+/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
+#error Architecture specific cpu local atomics already defined! Check your includes.
 #endif
 
+
+#ifndef local_atomic_exchange
+/* 
+ * Issuing a xchg instruction always implies lock prefix semantics.
+ * Therefore, it is cheaper to use a cmpxchg without a lock prefix 
+ * in a loop.
+ */
+#define local_atomic_exchange(pptr, new_val) \
+({ \
+        /* Use proper types and avoid name clashes */ \
+        typeof(*(pptr)) _exp_val_x; \
+        typeof(*(pptr)) _old_val_x; \
+        typeof(*(pptr)) _new_val_x = new_val; \
+        \
+        do { \
+                _exp_val_x = *pptr; \
+                _old_val_x = local_atomic_cas(pptr, _exp_val_x, _new_val_x); \
+        } while (_old_val_x != _exp_val_x); \
+        \
+        _old_val_x; \
+})
+
+#else
+/* Check if arch/atomic.h does not accidentally include /atomic.h .*/
+#error Architecture specific cpu local atomics already defined! Check your includes.
+#endif
+
+
+#endif
+
 /** @}
  */

kernel/arch/amd64/include/arch/cpu.h

@@ -73 +73 @@
         tss_t *tss;
         
+        unsigned int id; /** CPU's local, ie physical, APIC ID. */
+        
         size_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;

kernel/arch/amd64/include/arch/interrupt.h

@@ -69 +69 @@
 #define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
 #define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
+#define VECTOR_SMP_CALL_IPI       (IVT_FREEBASE + 3)
 
 extern void (* disable_irqs_function)(uint16_t);

kernel/arch/amd64/src/amd64.c

@@ -168 +168 @@
 }
 
-void arch_post_cpu_init()
+void arch_post_cpu_init(void)
 {
 #ifdef CONFIG_SMP

kernel/arch/amd64/src/cpu/cpu.c

@@ -158 +158 @@
 void cpu_print_report(cpu_t* m)
 {
-        printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
+        printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
             m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
-            m->arch.stepping, m->frequency_mhz);
+            m->arch.stepping, m->arch.id, m->frequency_mhz);
 }
 

kernel/arch/amd64/src/interrupt.c

@@ -55 +55 @@
 #include <symtab.h>
 #include <stacktrace.h>
+#include <smp/smp_call.h>
 
 /*
@@ -161 +162 @@
         trap_virtual_eoi();
         tlb_shootdown_ipi_recv();
+}
+
+static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
+{
+        trap_virtual_eoi();
+        smp_call_ipi_recv();
 }
 #endif
@@ -224 +231 @@
         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
             (iroutine_t) tlb_shootdown_ipi);
+        exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true, 
+                (iroutine_t) arch_smp_call_ipi_recv);
 #endif
 }