Changeset b0c2075 in mainline for kernel/arch


Ignore:
Timestamp:
2013-09-10T17:48:57Z (12 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
85147f3
Parents:
86733f3
Message:

new physical memory allocator supporting physical address constrains
the buddy allocator framework is retired and replaced by a two-level bitmap
the allocator can allocate an arbitrary number of frames, not only a power-of-two count

Caution: Change of semantics
The physical memory allocator no longer allocates naturally aligned blocks. If you require an aligned block, specify it as the constraint.

Location:
kernel/arch
Files:
12 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/arch/mm/page.h

    r86733f3 rb0c2075  
    5757
    5858/* Page table sizes for each level. */
    59 #define PTL0_SIZE_ARCH  ONE_FRAME
    60 #define PTL1_SIZE_ARCH  0
    61 #define PTL2_SIZE_ARCH  0
    62 #define PTL3_SIZE_ARCH  ONE_FRAME
     59#define PTL0_FRAMES_ARCH  1
     60#define PTL1_FRAMES_ARCH  1
     61#define PTL2_FRAMES_ARCH  1
     62#define PTL3_FRAMES_ARCH  1
    6363
    6464/* Macros calculating indices for each level. */

  • kernel/arch/amd64/include/arch/mm/page.h

    r86733f3 rb0c2075  
    6161
    6262/* Page table sizes for each level. */
    63 #define PTL0_SIZE_ARCH  ONE_FRAME
    64 #define PTL1_SIZE_ARCH  ONE_FRAME
    65 #define PTL2_SIZE_ARCH  ONE_FRAME
    66 #define PTL3_SIZE_ARCH  ONE_FRAME
     63#define PTL0_FRAMES_ARCH  1
     64#define PTL1_FRAMES_ARCH  1
     65#define PTL2_FRAMES_ARCH  1
     66#define PTL3_FRAMES_ARCH  1
    6767
    6868/* Macros calculating indices into page tables in each level. */

  • kernel/arch/arm32/include/arch/mm/page.h

    r86733f3 rb0c2075  
    7373
    7474/* Page table sizes for each level. */
    75 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    76 #define PTL1_SIZE_ARCH          0
    77 #define PTL2_SIZE_ARCH          0
    78 #define PTL3_SIZE_ARCH          ONE_FRAME
     75#define PTL0_FRAMES_ARCH  4
     76#define PTL1_FRAMES_ARCH  1
     77#define PTL2_FRAMES_ARCH  1
     78#define PTL3_FRAMES_ARCH  1
    7979
    8080/* Macros calculating indices into page tables for each level. */

  • kernel/arch/arm32/src/mm/page.c

    r86733f3 rb0c2075  
    6969#ifdef HIGH_EXCEPTION_VECTORS
    7070        /* Create mapping for exception table at high offset */
    71         uintptr_t ev_frame = frame_alloc(ONE_FRAME, FRAME_NONE, 0);
     71        uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0);
    7272        page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags);
    7373#else

  • kernel/arch/arm32/src/ras.c

    r86733f3 rb0c2075  
    5151void ras_init(void)
    5252{
    53         uintptr_t frame = frame_alloc(ONE_FRAME,
    54             FRAME_ATOMIC | FRAME_HIGHMEM, 0);
     53        uintptr_t frame =
     54            frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0);
    5555        if (!frame)
    56                 frame = frame_alloc(ONE_FRAME, FRAME_LOWMEM, 0);
     56                frame = frame_alloc(1, FRAME_LOWMEM, 0);
    5757       
    5858        ras_page = (uintptr_t *) km_map(frame,

  • kernel/arch/ia32/include/arch/mm/page.h

    r86733f3 rb0c2075  
    6666
    6767/* Page table sizes for each level. */
    68 #define PTL0_SIZE_ARCH  ONE_FRAME
    69 #define PTL1_SIZE_ARCH  0
    70 #define PTL2_SIZE_ARCH  0
    71 #define PTL3_SIZE_ARCH  ONE_FRAME
     68#define PTL0_FRAMES_ARCH  1
     69#define PTL1_FRAMES_ARCH  1
     70#define PTL2_FRAMES_ARCH  1
     71#define PTL3_FRAMES_ARCH  1
    7272
    7373/* Macros calculating indices for each level. */

  • kernel/arch/ia64/src/mm/vhpt.c

    r86733f3 rb0c2075  
    4242uintptr_t vhpt_set_up(void)
    4343{
    44         vhpt_base = (vhpt_entry_t *) PA2KA(frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
    45             FRAME_ATOMIC, 0));
     44        vhpt_base = (vhpt_entry_t *)
     45            PA2KA(frame_alloc(SIZE2FRAMES(VHPT_SIZE), FRAME_ATOMIC, 0));
    4646        if (!vhpt_base)
    4747                panic("Kernel configured with VHPT but no memory for table.");
    … …  
    8383void vhpt_invalidate_all()
    8484{
    85         memsetb(vhpt_base, 1 << VHPT_WIDTH, 0);
     85        memsetb(vhpt_base, VHPT_SIZE, 0);
    8686}
    8787

  • kernel/arch/mips32/include/arch/mm/page.h

    r86733f3 rb0c2075  
    7878
    7979/* Macros describing size of page tables in each level. */
    80 #define PTL0_SIZE_ARCH          ONE_FRAME
    81 #define PTL1_SIZE_ARCH          0
    82 #define PTL2_SIZE_ARCH          0
    83 #define PTL3_SIZE_ARCH          ONE_FRAME
     80#define PTL0_FRAMES_ARCH  1
     81#define PTL1_FRAMES_ARCH  1
     82#define PTL2_FRAMES_ARCH  1
     83#define PTL3_FRAMES_ARCH  1
    8484
    8585/* Macros calculating entry indices for each level. */

  • kernel/arch/mips32/src/mm/tlb.c

    r86733f3 rb0c2075  
    4848#include <symtab.h>
    4949
    50 #define PFN_SHIFT       12
    51 #define VPN_SHIFT       12
    52 #define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
    53 #define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
    54 #define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
    55 #define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
    56 #define PFN2ADDR(pfn)   ((pfn) << PFN_SHIFT)
    57 
    58 #define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1)
    59        
     50#define PFN_SHIFT  12
     51#define VPN_SHIFT  12
     52
     53#define ADDR2HI_VPN(a)   ((a) >> VPN_SHIFT)
     54#define ADDR2HI_VPN2(a)  (ADDR2HI_VPN((a)) >> 1)
     55
     56#define HI_VPN2ADDR(vpn)    ((vpn) << VPN_SHIFT)
     57#define HI_VPN22ADDR(vpn2)  (HI_VPN2ADDR(vpn2) << 1)
     58
     59#define LO_PFN2ADDR(pfn)  ((pfn) << PFN_SHIFT)
     60
     61#define BANK_SELECT_BIT(a)  (((a) >> PAGE_WIDTH) & 1)
    6062
    6163/** Initialize TLB.
    … …  
    266268{
    267269        hi->value = 0;
    268         hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
     270        hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
    269271        hi->asid = asid;
    270272}
    … …  
    295297               
    296298                printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
    297                     i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
    298                     lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
     299                    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
     300                    lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));
    299301                printf("                               %1u%1u%1u%1u  %0#10x\n",
    300                     lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
     302                    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
    301303        }
    302304       

  • kernel/arch/ppc32/include/arch/mm/page.h

    r86733f3 rb0c2075  
    7070
    7171/* Page table sizes for each level. */
    72 #define PTL0_SIZE_ARCH  ONE_FRAME
    73 #define PTL1_SIZE_ARCH  0
    74 #define PTL2_SIZE_ARCH  0
    75 #define PTL3_SIZE_ARCH  ONE_FRAME
     72#define PTL0_FRAMES_ARCH  1
     73#define PTL1_FRAMES_ARCH  1
     74#define PTL2_FRAMES_ARCH  1
     75#define PTL3_FRAMES_ARCH  1
    7676
    7777/* Macros calculating indices into page tables on each level. */

  • kernel/arch/sparc64/src/mm/sun4u/as.c

    r86733f3 rb0c2075  
    6363{
    6464#ifdef CONFIG_TSB
    65         /*
    66          * The order must be calculated with respect to the emulated
    67          * 16K page size.
    68          *
    69          */
    70         uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
    71             sizeof(tsb_entry_t)) >> FRAME_WIDTH);
    72        
    73         uintptr_t tsb = PA2KA(frame_alloc(order, flags, 0));
     65        size_t frames = SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
     66            sizeof(tsb_entry_t));
     67       
     68        uintptr_t tsb = PA2KA(frame_alloc(frames, flags, 0));
    7469        if (!tsb)
    7570                return -1;
    7671       
    7772        as->arch.itsb = (tsb_entry_t *) tsb;
    78         as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
    79             sizeof(tsb_entry_t));
     73        as->arch.dtsb = (tsb_entry_t *) (tsb +
     74            ITSB_ENTRY_COUNT * sizeof(tsb_entry_t));
    8075       
    8176        memsetb(as->arch.itsb,

  • kernel/arch/sparc64/src/mm/sun4v/as.c

    r86733f3 rb0c2075  
    6666{
    6767#ifdef CONFIG_TSB
    68         uint8_t order = fnzb32(
    69                 (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH);
     68        size_t frames =
     69            SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
    7070       
    71         uintptr_t tsb = frame_alloc(order, flags, 0);
     71        uintptr_t tsb = frame_alloc(frames, flags, 0);
    7272        if (!tsb)
    7373                return -1;
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