source: mainline/kernel/arch/sparc64/src/mm/sun4v/as.c@ b0c2075

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b0c2075 was b0c2075, checked in by Martin Decky <martin@…>, 12 years ago

new physical memory allocator supporting physical address constrains
the buddy allocator framework is retired and replaced by a two-level bitmap
the allocator can allocate an arbitrary number of frames, not only a power-of-two count

Caution: Change of semantics
The physical memory allocator no longer allocates naturally aligned blocks. If you require an aligned block, specify it as the constraint.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * Copyright (c) 2009 Pavel Rimsky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup sparc64mm
31 * @{
32 */
33/** @file
34 */
35
36#include <arch/mm/as.h>
37#include <arch/mm/pagesize.h>
38#include <arch/mm/tlb.h>
39#include <genarch/mm/page_ht.h>
40#include <genarch/mm/asid_fifo.h>
41#include <debug.h>
42#include <config.h>
43#include <arch/sun4v/hypercall.h>
44
45#ifdef CONFIG_TSB
46
47#include <arch/mm/tsb.h>
48#include <arch/asm.h>
49#include <mm/frame.h>
50#include <bitops.h>
51#include <macros.h>
52#include <memstr.h>
53
54#endif /* CONFIG_TSB */
55
56/** Architecture dependent address space init. */
57void as_arch_init(void)
58{
59 if (config.cpu_active == 1) {
60 as_operations = &as_ht_operations;
61 asid_fifo_init();
62 }
63}
64
65int as_constructor_arch(as_t *as, unsigned int flags)
66{
67#ifdef CONFIG_TSB
68 size_t frames =
69 SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
70
71 uintptr_t tsb = frame_alloc(frames, flags, 0);
72 if (!tsb)
73 return -1;
74
75 as->arch.tsb_description.page_size = PAGESIZE_8K;
76 as->arch.tsb_description.associativity = 1;
77 as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT;
78 as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K;
79 as->arch.tsb_description.tsb_base = tsb;
80 as->arch.tsb_description.reserved = 0;
81 as->arch.tsb_description.context = 0;
82
83 memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base),
84 TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0);
85#endif
86
87 return 0;
88}
89
90int as_destructor_arch(as_t *as)
91{
92#ifdef CONFIG_TSB
93 size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
94 frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
95
96 return cnt;
97#else
98 return 0;
99#endif
100}
101
102int as_create_arch(as_t *as, unsigned int flags)
103{
104#ifdef CONFIG_TSB
105 tsb_invalidate(as, 0, (size_t) -1);
106#endif
107
108 return 0;
109}
110
111/** Perform sparc64-specific tasks when an address space becomes active on the
112 * processor.
113 *
114 * Install ASID and map TSBs.
115 *
116 * @param as Address space.
117 *
118 */
119void as_install_arch(as_t *as)
120{
121 mmu_secondary_context_write(as->asid);
122
123#ifdef CONFIG_TSB
124 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
125
126 ASSERT(as->arch.tsb_description.tsb_base);
127 uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
128
129 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
130 /*
131 * TSBs were allocated from memory not covered
132 * by the locked 4M kernel DTLB entry. We need
133 * to map both TSBs explicitly.
134 *
135 */
136 mmu_demap_page(tsb, 0, MMU_FLAG_DTLB);
137 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
138 }
139
140 __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description)));
141#endif
142}
143
144/** Perform sparc64-specific tasks when an address space is removed from the
145 * processor.
146 *
147 * Demap TSBs.
148 *
149 * @param as Address space.
150 *
151 */
152void as_deinstall_arch(as_t *as)
153{
154 /*
155 * Note that we don't and may not lock the address space. That's ok
156 * since we only read members that are currently read-only.
157 *
158 * Moreover, the as->asid is protected by asidlock, which is being held.
159 *
160 */
161
162#ifdef CONFIG_TSB
163 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
164
165 ASSERT(as->arch.tsb_description.tsb_base);
166
167 uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base);
168
169 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
170 /*
171 * TSBs were allocated from memory not covered
172 * by the locked 4M kernel DTLB entry. We need
173 * to demap the entry installed by as_install_arch().
174 *
175 */
176 __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB);
177 }
178#endif
179}
180
181/** @}
182 */
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