Changeset ae7d03c in mainline for uspace/drv


Ignore:
Timestamp:
2018-05-10T13:39:19Z (7 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
e8975278
Parents:
b277bef
git-author:
Jiri Svoboda <jiri@…> (2018-05-10 07:38:12)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-10 13:39:19)
Message:

Selected ccheck-proposed comment fixes.

Location:
uspace/drv
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/audio/hdaudio/hdactl.c

    rb277bef rae7d03c  
    516516            hda_reg16_read(&hda->regs->statests));
    517517        /**
    518           * Clear STATESTS bits so they don't generate an interrupt later
    519           * when we enable interrupts.
    520           */
     518         * Clear STATESTS bits so they don't generate an interrupt later
     519         * when we enable interrupts.
     520         */
    521521        hda_reg16_write(&hda->regs->statests, 0x7f);
    522522

  • uspace/drv/block/ahci/ahci_hw.h

    rb277bef rae7d03c  
    216216typedef union {
    217217        struct {
    218         /** Indicates the completion status of BIST
    219         * non-zero value indicates a failure.
    220         */
    221         unsigned int cc : 4;
    222         /** Reserved. */
    223         unsigned int reserved : 2;
    224         /** Software sets this bit to 1 to invoke BIST,
    225         * the HBA clears this bit to 0 when BIST is complete.
    226         */
    227         unsigned int sb : 1;
    228         /** BIST capable. */
    229         unsigned int bc : 1;
     218                /** Indicates the completion status of BIST
     219                * non-zero value indicates a failure.
     220                */
     221                unsigned int cc : 4;
     222                /** Reserved. */
     223                unsigned int reserved : 2;
     224                /** Software sets this bit to 1 to invoke BIST,
     225                * the HBA clears this bit to 0 when BIST is complete.
     226                */
     227                unsigned int sb : 1;
     228                /** BIST capable. */
     229                unsigned int bc : 1;
    230230        };
    231231        uint8_t u8;
    … …  
    252252
    253253/** AHCI PCI register Subsystem Identifiers. */
    254 typedef struct
    255 {
     254typedef struct {
    256255        /** Sub system vendor identifier. */
    257256        uint8_t ssvid;
    … …  
    261260
    262261/** AHCI PCI registers Expansion ROM Base Address. */
    263 typedef struct
    264 {
     262typedef struct {
    265263        /** Indicates the base address of the HBA expansion ROM. */
    266264        uint32_t u32;
    … …  
    268266
    269267/** AHCI PCI register Capabilities Pointer. */
    270 typedef struct
    271 {
     268typedef struct {
    272269        /** Indicates the first capability pointer offset. */
    273270        uint8_t u8;
    … …  
    275272
    276273/** AHCI PCI register Interrupt Information. */
    277 typedef struct
    278 {
     274typedef struct {
    279275        /* Software written value to indicate which interrupt vector
    280276         * the interrupt is connected to.
    … …  
    286282
    287283/** AHCI PCI register Min Grant (Optional). */
    288 typedef struct
    289 {
     284typedef struct {
    290285        /** Indicates the minimum grant time that the device
    291286         * wishes grant asserted.
    … …  
    295290
    296291/** AHCI PCI register Max Latency (Optional). */
    297 typedef struct
    298 {
     292typedef struct {
    299293        /** Indicates the maximum latency that the device can withstand. */
    300294        uint8_t u8;
    … …  
    431425
    432426/** AHCI Memory register Command completion coalescing ports. */
    433 typedef struct
    434 {
     427typedef struct {
    435428        /** If a bit is set to 1, the corresponding port is
    436429         * part of the command completion coalescing feature.
    … …  
    440433
    441434/** AHCI Memory register Enclosure management location. */
    442 typedef struct
    443 {
     435typedef struct {
    444436        /** Size of the transmit message buffer area in dwords. */
    445437        uint16_t sz;
    … …  
    525517
    526518/** AHCI Memory register Generic Host Control. */
    527 typedef struct
    528 {
     519typedef struct {
    529520        /** Host Capabilities */
    530521        uint32_t cap;
    … …  
    942933
    943934/** AHCI Memory register Port. */
    944 typedef volatile struct
    945 {
     935typedef volatile struct {
    946936        /** Port x Command List Base Address. */
    947937        uint32_t pxclb;
    … …  
    10101000        /** Physical Region Descriptor Byte Count. */
    10111001        uint32_t bytesprocessed;
    1012          /** Command Table Descriptor Base Address. */
     1002        /** Command Table Descriptor Base Address. */
    10131003        uint32_t cmdtable;
    10141004        /** Command Table Descriptor Base Address Upper 32-bits. */

  • uspace/drv/block/ddisk/ddisk.c

    rb277bef rae7d03c  
    495495
    496496        /*
    497          * Register IRQ handler.
    498          */
     497         * Register IRQ handler.
     498         */
    499499        ddisk_regs_t *res_phys = (ddisk_regs_t *) res.base;
    500500        ddisk_irq_pio_ranges[0].base = res.base;

  • uspace/drv/bus/pci/pciintel/pci.c

    rb277bef rae7d03c  
    267267                 * architectures do not support shorter PIO reads offset from
    268268                 * this register.
    269                  */
     269                 */
    270270                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
    271271        } else {
    … …  
    301301         * Some architectures do not support shorter PIO writes offset from this
    302302         * register.
    303          */
     303         */
    304304
    305305        if (len < 4) {
    306306                /*
    307                  * We have fewer than full 32-bits, so we need to read the
    308                  * missing bits first.
    309                  */
     307                 * We have fewer than full 32-bits, so we need to read the
     308                 * missing bits first.
     309                 */
    310310                if (bus->conf_addr_reg) {
    311311                        pio_write_32(bus->conf_addr_reg,
    … …  
    534534
    535535        /*
    536          * Unimplemented BARs read back as all 0's.
    537          */
     536         * Unimplemented BARs read back as all 0's.
     537         */
    538538        if (!bar)
    539539                return addr + (addrw64 ? 8 : 4);

  • uspace/drv/bus/usb/xhci/hw_struct/trb.h

    rb277bef rae7d03c  
    8080        /*
    8181         * Reserved: 24-31
    82         */
     82         */
    8383
    8484        /*

  • uspace/drv/nic/ar9271/ar9271.c

    rb277bef rae7d03c  
    801801         * This should initiate creating confirmation message in
    802802         * device side buffer which we will check in htc_check_ready function.
    803         */
     803         */
    804804        usb_pipe_t *ctrl_pipe = usb_device_get_default_pipe(usb_device);
    805805        errno_t rc = usb_control_request_set(ctrl_pipe,

  • uspace/drv/nic/rtl8139/driver.c

    rb277bef rae7d03c  
    9494
    9595#ifndef RXBUF_SIZE_FLAGS
    96         /** Flags for receiver buffer - 16kB default */
     96/** Flags for receiver buffer - 16kB default */
    9797#define RXBUF_SIZE_FLAGS RTL8139_RXFLAGS_SIZE_16
    9898#endif

  • uspace/drv/nic/rtl8169/driver.c

    rb277bef rae7d03c  
    12051205
    12061206/** Main function of RTL8169 driver
    1207 *
     1207 *
    12081208 *  Just initialize the driver structures and
    12091209 *  put it into the device drivers interface

  • uspace/drv/platform/malta/malta.c

    rb277bef rae7d03c  
    233233
    234234        /*
    235          * We need to disable byte swapping of the outgoing and incoming
    236          * PCI data, because the PCI driver assumes no byte swapping behind
    237          * the scenes and takes care of it itself.
    238          */
     235         * We need to disable byte swapping of the outgoing and incoming
     236         * PCI data, because the PCI driver assumes no byte swapping behind
     237         * the scenes and takes care of it itself.
     238         */
    239239        ret = pio_enable((void *) GT_BASE, GT_SIZE, (void **) &gt);
    240240        if (ret != EOK)
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