Changeset add04f7 in mainline for kernel/arch/ia32/include/barrier.h

Timestamp:

2009-03-03T15:20:49Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f24d300

Parents:

deca67b

Message:

better inline assembler readability using the new symbolic syntax

File:

• kernel/arch/ia32/include/barrier.h (modified) (4 diffs)

kernel/arch/ia32/include/barrier.h

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -47 +47 @@
  */
 
-#define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
 static inline void cpuid_serialization(void)
@@ -60 +60 @@
 
 #if defined(CONFIG_FENCES_P4)
-#       define memory_barrier()         asm volatile ("mfence\n" ::: "memory")
-#       define read_barrier()           asm volatile ("lfence\n" ::: "memory")
-#       ifdef CONFIG_WEAK_MEMORY
-#               define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-#       else
-#               define write_barrier()  asm volatile( "" ::: "memory");
-#       endif
+        #define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
+        #define read_barrier()    asm volatile ("lfence\n" ::: "memory")
+        #ifdef CONFIG_WEAK_MEMORY
+                #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+        #else
+                #define write_barrier()  asm volatile ("" ::: "memory");
+        #endif
 #elif defined(CONFIG_FENCES_P3)
-#       define memory_barrier()         cpuid_serialization()
-#       define read_barrier()           cpuid_serialization()
-#       ifdef CONFIG_WEAK_MEMORY
-#               define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-#       else
-#               define write_barrier()  asm volatile( "" ::: "memory");
-#       endif
+        #define memory_barrier()  cpuid_serialization()
+        #define read_barrier()    cpuid_serialization()
+        #ifdef CONFIG_WEAK_MEMORY
+                #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+        #else
+                #define write_barrier()  asm volatile ("" ::: "memory");
+        #endif
 #else
-#       define memory_barrier()         cpuid_serialization()
-#       define read_barrier()           cpuid_serialization()
-#       ifdef CONFIG_WEAK_MEMORY
-#               define write_barrier()  cpuid_serialization()
-#       else
-#               define write_barrier()  asm volatile( "" ::: "memory");
-#       endif
+        #define memory_barrier()  cpuid_serialization()
+        #define read_barrier()    cpuid_serialization()
+        #ifdef CONFIG_WEAK_MEMORY
+                #define write_barrier()  cpuid_serialization()
+        #else
+                #define write_barrier()  asm volatile ("" ::: "memory");
+        #endif
 #endif
 
@@ -91 +91 @@
  * sufficient for them to drain to the D-cache).
  */
-#define smc_coherence(a)                write_barrier()
-#define smc_coherence_block(a, l)       write_barrier()
+#define smc_coherence(a)           write_barrier()
+#define smc_coherence_block(a, l)  write_barrier()
 
 #endif