Changeset a83a802 in mainline for arch/ia32/src/smp/apic.c
- Timestamp:
- 2005-11-23T13:28:17Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8418c7d
- Parents:
- 607c5f9
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/src/smp/apic.c
r607c5f9 ra83a802 41 41 42 42 /* 43 * This is functional, far-from-general-enough interface to the APIC. 44 * Advanced Programmable Interrupt Controller for MP systems. 43 * Advanced Programmable Interrupt Controller for SMP systems. 45 44 * Tested on: 46 45 * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs … … 83 82 io_apic_disable_irqs(0xffff); 84 83 trap_register(VECTOR_CLK, l_apic_timer_interrupt); 85 for (i= 1; i<16; i++) {84 for (i=0; i<16; i++) { 86 85 int pin; 87 86 88 if ((pin = mps_irq_to_pin(i)) != -1) 89 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); 87 if ((pin = smp_irq_to_pin(i)) != -1) { 88 io_apic_change_ioredtbl(pin,0xff,IVT_IRQBASE+i,LOPRI); 89 } 90 90 } 91 91 … … 353 353 void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) 354 354 { 355 __u32 reglo, reghi;355 io_redirection_reg_t reg; 356 356 int dlvr = 0; 357 357 358 358 if (flags & LOPRI) 359 dlvr = 1; 360 361 reglo = io_apic_read(IOREDTBL + signal*2); 362 reghi = io_apic_read(IOREDTBL + signal*2 + 1); 363 364 reghi &= ~0x0f000000; 365 reghi |= (dest<<24); 366 367 reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */ 368 reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v; 369 370 io_apic_write(IOREDTBL + signal*2, reglo); 371 io_apic_write(IOREDTBL + signal*2 + 1, reghi); 359 dlvr = DELMOD_LOWPRI; 360 361 362 reg.lo = io_apic_read(IOREDTBL + signal*2); 363 reg.hi = io_apic_read(IOREDTBL + signal*2 + 1); 364 365 reg.dest = dest; 366 reg.destmod = DESTMOD_LOGIC; 367 reg.trigger_mode = TRIGMOD_EDGE; 368 reg.intpol = POLARITY_HIGH; 369 reg.delmod = dlvr; 370 reg.intvec = v; 371 372 io_apic_write(IOREDTBL + signal*2, reg.lo); 373 io_apic_write(IOREDTBL + signal*2 + 1, reg.hi); 372 374 } 373 375 374 376 void io_apic_disable_irqs(__u16 irqmask) 375 377 { 376 i nt i,pin;377 __u32 reglo;378 io_redirection_reg_t reg; 379 int i, pin; 378 380 379 381 for (i=0;i<16;i++) { … … 383 385 * mapping for the respective IRQ number. 384 386 */ 385 pin = mps_irq_to_pin(i);387 pin = smp_irq_to_pin(i); 386 388 if (pin != -1) { 387 reg lo = io_apic_read(IOREDTBL + pin*2);388 reg lo |= (1<<16);389 io_apic_write(IOREDTBL + pin*2, reglo);389 reg.lo = io_apic_read(IOREDTBL + pin*2); 390 reg.masked = true; 391 io_apic_write(IOREDTBL + pin*2, reg.lo); 390 392 } 391 393 … … 396 398 void io_apic_enable_irqs(__u16 irqmask) 397 399 { 398 int i, pin;399 __u32 reglo;400 int i, pin; 401 io_redirection_reg_t reg; 400 402 401 403 for (i=0;i<16;i++) { … … 405 407 * mapping for the respective IRQ number. 406 408 */ 407 pin = mps_irq_to_pin(i);409 pin = smp_irq_to_pin(i); 408 410 if (pin != -1) { 409 reg lo = io_apic_read(IOREDTBL + pin*2);410 reg lo &= ~(1<<16);411 io_apic_write(IOREDTBL + pin*2, reglo);411 reg.lo = io_apic_read(IOREDTBL + pin*2); 412 reg.masked = false; 413 io_apic_write(IOREDTBL + pin*2, reg.lo); 412 414 } 413 415
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