Changeset a7961271 in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2006-08-26T18:42:11Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c8ea4a8b
Parents:
f47fd19
Message:

sparc64 work.
Bunch of changes in preparation for sparc64 mm and userspace support.
Fix alignment of hardcoded_* variables in linker script.

Location:
kernel/arch/sparc64/include
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch.h

    rf47fd19 ra7961271  
    3636#define __sparc64_ARCH_H__
    3737
     38#define ASI_AIUP        0x10    /** Access to primary context with user privileges. */
     39#define ASI_AIUS        0x11    /** Access to secondary context with user privileges. */
     40
    3841#endif
    3942

  • kernel/arch/sparc64/include/interrupt.h

    rf47fd19 ra7961271  
    4545#define IVT_FIRST       1
    4646
    47 /* Dummy macros. */
    48 #define IRQ_KBD         2
    49 #define VECTOR_KBD      IRQ_KBD
    50 
    51 #define trap_virtual_enable_irqs(x)
    52 #define trap_virtual_eoi()
    53 
    5447struct istate {
    5548        uint64_t        pstate;

  • kernel/arch/sparc64/include/regdef.h

    rf47fd19 ra7961271  
    3636#define KERN_sparc64_REGDEF_H_
    3737
    38 #define PSTATE_IE_BIT   2
    39 #define PSTATE_AM_BIT   8
     38#define PSTATE_IE_BIT   (1<<1)
     39#define PSTATE_AM_BIT   (1<<3)
    4040
    4141#define PSTATE_AG_BIT   (1<<0)
    … …  
    4343#define PSTATE_MG_BIT   (1<<10)
    4444
     45#define PSTATE_PRIV_BIT (1<<2)
     46
     47#define TSTATE_PSTATE_SHIFT     8
     48#define TSTATE_PRIV_BIT         (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT)
     49
     50#define TSTATE_CWP_MASK         0x1f
     51
    4552#endif
    4653

  • kernel/arch/sparc64/include/trap/interrupt.h

    rf47fd19 ra7961271  
    8080#ifdef __ASM__
    8181.macro INTERRUPT_LEVEL_N_HANDLER n
    82         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
    83         mov \n - 1, %o0
     82        mov \n - 1, %g2
    8483        PREEMPTIBLE_HANDLER exc_dispatch
    8584.endm

  • kernel/arch/sparc64/include/trap/mmu.h

    rf47fd19 ra7961271  
    3939
    4040#include <arch/stack.h>
     41#include <arch/regdef.h>
    4142#include <arch/mm/tlb.h>
    4243#include <arch/mm/mmu.h>
    … …  
    6061.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
    6162        /*
    62          * First, test if it is the portion of the kernel address space
     63         * First, try to refill TLB from TSB.
     64         */
     65        ! TODO
     66
     67        /*
     68         * Second, test if it is the portion of the kernel address space
    6369         * which is faulting. If that is the case, immediately create
    6470         * identity mapping for that page in DTLB. VPN 0 is excluded from
    … …  
    6773         * Note that branch-delay slots are used in order to save space.
    6874         */
     750:
    6976        mov VA_DMMU_TAG_ACCESS, %g1
    7077        ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
    … …  
    7582        bz 0f                                           ! page address is zero
    7683
    77         /*
    78          * Create and insert the identity-mapped entry for
    79          * the faulting kernel page.
    80          */
    81        
    8284        or %g3, (TTE_CP|TTE_P|TTE_W), %g2               ! 8K pages are the default (encoded as 0)
    8385        set 1, %g3
    … …  
    8789        retry
    8890
     91        /*
     92         * Third, catch and handle special cases when the trap is caused by
     93         * some register window trap handler.
     94         */
    89950:
    90         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp                                             
     96        ! TODO
     97
     980:
     99        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    91100        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
    92101.endm

  • kernel/arch/sparc64/include/trap/regwin.h

    rf47fd19 ra7961271  
    3939
    4040#include <arch/stack.h>
     41#include <arch/arch.h>
    4142
    4243#define TT_CLEAN_WINDOW                 0x24
    … …  
    5051#define FILL_HANDLER_SIZE               REGWIN_HANDLER_SIZE
    5152
    52 /** Window Save Area offsets. */
     53#define NWINDOW         8
     54
     55/* Window Save Area offsets. */
    5356#define L0_OFFSET       0
    5457#define L1_OFFSET       8
    … …  
    6972
    7073#ifdef __ASM__
    71 .macro SPILL_NORMAL_HANDLER
     74
     75/*
     76 * Macro used by the nucleus and the primary context 0 during normal and other spills.
     77 */
     78.macro SPILL_NORMAL_HANDLER_KERNEL
    7279        stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
    7380        stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
    … …  
    9097.endm
    9198
    92 .macro FILL_NORMAL_HANDLER
     99/*
     100 * Macro used by the userspace during normal spills.
     101 */
     102.macro SPILL_NORMAL_HANDLER_USERSPACE
     103        wr ASI_AIUP, %asi
     104        stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
     105        stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
     106        stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
     107        stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
     108        stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
     109        stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
     110        stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
     111        stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
     112        stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
     113        stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
     114        stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
     115        stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
     116        stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
     117        stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
     118        stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
     119        stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
     120        saved
     121        retry
     122.endm
     123
     124/*
     125 * Macro used by the userspace during other spills.
     126 */
     127.macro SPILL_OTHER_HANDLER_USERSPACE
     128        wr ASI_AIUS, %asi
     129        stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
     130        stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
     131        stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
     132        stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
     133        stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
     134        stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
     135        stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
     136        stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
     137        stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
     138        stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
     139        stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
     140        stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
     141        stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
     142        stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
     143        stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
     144        stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
     145        saved
     146        retry
     147.endm
     148
     149
     150/*
     151 * Macro used by the nucleus and the primary context 0 during normal fills.
     152 */
     153.macro FILL_NORMAL_HANDLER_KERNEL
    93154        ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
    94155        ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
    … …  
    107168        ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
    108169        ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
     170        restored
     171        retry
     172.endm
     173
     174/*
     175 * Macro used by the userspace during normal fills.
     176 */
     177.macro FILL_NORMAL_HANDLER_USERSPACE
     178        wr ASI_AIUP, %asi
     179        ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
     180        ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
     181        ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
     182        ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
     183        ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
     184        ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
     185        ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
     186        ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
     187        ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
     188        ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
     189        ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
     190        ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
     191        ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
     192        ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
     193        ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
     194        ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
     195        restored
     196        retry
     197.endm
     198
     199/*
     200 * Macro used by the userspace during other fills.
     201 */
     202.macro FILL_OTHER_HANDLER_USERSPACE
     203        wr ASI_AIUS, %asi
     204        ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
     205        ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
     206        ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
     207        ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
     208        ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
     209        ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
     210        ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
     211        ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
     212        ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
     213        ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
     214        ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
     215        ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
     216        ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
     217        ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
     218        ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
     219        ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
    109220        restored
    110221        retry

  • kernel/arch/sparc64/include/trap/trap_table.h

    rf47fd19 ra7961271  
    8686#define SAVED_TPC       -(2*8)
    8787#define SAVED_TNPC      -(3*8)
    88 #define SAVED_PSTATE    -(4*8)
    8988
    9089.macro PREEMPTIBLE_HANDLER f
    91         set \f, %l0
     90        sethi %hi(\f), %g1
    9291        b preemptible_handler
    93         nop
     92        or %g1, %lo(\f), %g1
    9493.endm
    9594
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