Changeset f47fd19 in mainline for kernel/arch/sparc64/include
- Timestamp:
- 2006-08-21T13:36:34Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a7961271
- Parents:
- ee289cf0
- Location:
- kernel/arch/sparc64/include
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/context.h
ree289cf0 rf47fd19 27 27 */ 28 28 29 29 /** @addtogroup sparc64 30 30 * @{ 31 31 */ … … 90 90 #endif 91 91 92 92 /** @} 93 93 */ 94 -
kernel/arch/sparc64/include/context_offset.h
ree289cf0 rf47fd19 21 21 #define OFFSET_CLEANWIN 0x98 22 22 23 /** @}24 */25 -
kernel/arch/sparc64/include/interrupt.h
ree289cf0 rf47fd19 27 27 */ 28 28 29 29 /** @addtogroup sparc64interrupt sparc64 30 30 * @ingroup interrupt 31 31 * @{ … … 53 53 54 54 struct istate { 55 uint64_t pstate; 56 uint64_t tnpc; 57 uint64_t tpc; 58 uint64_t tstate; 55 59 }; 56 60 … … 75 79 #endif 76 80 77 81 /** @} 78 82 */ 79 -
kernel/arch/sparc64/include/mm/tlb.h
ree289cf0 rf47fd19 67 67 /* TLB Tag Access shifts */ 68 68 #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 69 #define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1) 69 70 #define TLB_TAG_ACCESS_VPN_SHIFT 13 70 71 … … 108 109 struct { 109 110 uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ 110 unsigned context : 13; /**< Context identifier. */111 unsigned context : 13; /**< Context identifier. */ 111 112 } __attribute__ ((packed)); 112 113 }; … … 119 120 uint64_t value; 120 121 struct { 121 uint64_t vpn: 51; 122 uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ 122 123 unsigned : 6; /**< Ignored. */ 123 124 unsigned type : 1; /**< The type of demap operation. */ … … 132 133 uint64_t value; 133 134 struct { 134 unsigned long : 39; /**< Implementation dependent. */ 135 unsigned nf : 1; /**< Nonfaulting load. */ 135 unsigned long : 40; /**< Implementation dependent. */ 136 136 unsigned asi : 8; /**< ASI. */ 137 unsigned tm : 1; /**< TLB miss. */ 138 unsigned : 1; 137 unsigned : 2; 139 138 unsigned ft : 7; /**< Fault type. */ 140 139 unsigned e : 1; /**< Side-effect bit. */ … … 426 425 } 427 426 428 extern void fast_instruction_access_mmu_miss( void);429 extern void fast_data_access_mmu_miss( void);430 extern void fast_data_access_protection( void);427 extern void fast_instruction_access_mmu_miss(int n, istate_t *istate); 428 extern void fast_data_access_mmu_miss(int n, istate_t *istate); 429 extern void fast_data_access_protection(int n, istate_t *istate); 431 430 432 431 extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); -
kernel/arch/sparc64/include/regdef.h
ree289cf0 rf47fd19 39 39 #define PSTATE_AM_BIT 8 40 40 41 #define PSTATE_AG_BIT (1<<0) 42 #define PSTATE_IG_BIT (1<<11) 43 #define PSTATE_MG_BIT (1<<10) 44 41 45 #endif 42 46 -
kernel/arch/sparc64/include/trap/interrupt.h
ree289cf0 rf47fd19 82 82 save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp 83 83 mov \n - 1, %o0 84 mov %fp, %o185 84 PREEMPTIBLE_HANDLER exc_dispatch 86 85 .endm -
kernel/arch/sparc64/include/trap/mmu.h
ree289cf0 rf47fd19 39 39 40 40 #include <arch/stack.h> 41 #include <arch/mm/tlb.h> 42 #include <arch/mm/mmu.h> 43 #include <arch/mm/tte.h> 41 44 42 45 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 … … 56 59 57 60 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER 58 save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp 59 call fast_data_access_mmu_miss 60 nop 61 restore 61 /* 62 * First, test if it is the portion of the kernel address space 63 * which is faulting. If that is the case, immediately create 64 * identity mapping for that page in DTLB. VPN 0 is excluded from 65 * this treatment. 66 * 67 * Note that branch-delay slots are used in order to save space. 68 */ 69 mov VA_DMMU_TAG_ACCESS, %g1 70 ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN 71 set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 72 andcc %g1, %g2, %g3 ! get Context 73 bnz 0f ! Context is non-zero 74 andncc %g1, %g2, %g3 ! get page address into %g3 75 bz 0f ! page address is zero 76 77 /* 78 * Create and insert the identity-mapped entry for 79 * the faulting kernel page. 80 */ 81 82 or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0) 83 set 1, %g3 84 sllx %g3, TTE_V_SHIFT, %g3 85 or %g2, %g3, %g2 86 stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page 62 87 retry 88 89 0: 90 save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp 91 PREEMPTIBLE_HANDLER fast_data_access_mmu_miss 63 92 .endm 64 93 -
kernel/arch/sparc64/include/trap/trap_table.h
ree289cf0 rf47fd19 78 78 .endm 79 79 80 /* 81 * The following needs to be in sync with the 82 * definition of the istate structure. 83 */ 80 84 #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE (STACK_WINDOW_SAVE_AREA_SIZE+(4*8)) 81 85 #define SAVED_TSTATE -(1*8)
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