Changeset a35b458 in mainline for kernel/arch/sparc64/src/fpu_context.c
- Timestamp:
- 2018-03-02T20:10:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/fpu_context.c
r3061bc1 ra35b458 67 67 * GCC (4.1.1) can't handle more than 30 operands in one asm statement. 68 68 */ 69 69 70 70 asm volatile ( 71 71 "std %%f32, %0\n" … … 90 90 "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) 91 91 ); 92 92 93 93 asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); 94 94 } … … 119 119 "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) 120 120 ); 121 121 122 122 /* 123 123 * We need to split loading of the floating-point registers because 124 124 * GCC (4.1.1) can't handle more than 30 operands in one asm statement. 125 125 */ 126 126 127 127 asm volatile ( 128 128 "ldd %0, %%f32\n" … … 148 148 "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) 149 149 ); 150 150 151 151 asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); 152 152 } … … 155 155 { 156 156 pstate_reg_t pstate; 157 157 158 158 pstate.value = pstate_read(); 159 159 pstate.pef = true; … … 164 164 { 165 165 pstate_reg_t pstate; 166 166 167 167 pstate.value = pstate_read(); 168 168 pstate.pef = false;
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