- Timestamp:
- 2018-05-22T10:36:58Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a4eb3ba2
- Parents:
- 4f8772d4
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-21 17:36:30)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-22 10:36:58)
- Location:
- kernel
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/arch/cp15.h
r4f8772d4 r904b1bc 40 40 41 41 /** See ARM Architecture reference manual ch. B3.17.1 page B3-1456 42 * for the list */ 42 * for the list 43 */ 43 44 44 45 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \ … … 183 184 CCSIDR_LINESIZE_MASK = 0x7, 184 185 CCSIDR_LINESIZE_SHIFT = 0, 186 }; 187 185 188 #define CCSIDR_SETS(val) \ 186 189 (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1) … … 190 193 #define CCSIDR_LINESIZE_LOG(val) \ 191 194 (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2) 192 }; 195 193 196 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); 194 197 … … 206 209 CLIDR_UNI_CACHE = 0x4, 207 210 CLIDR_CACHE_MASK = 0x7, 211 }; 212 208 213 /** levels counted from 0 */ 209 214 #define CLIDR_CACHE(level, val) ((val >> (level * 3)) & CLIDR_CACHE_MASK) 210 }; 215 211 216 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); 212 217 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */ … … 225 230 226 231 /* System control registers */ 227 /* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference 228 * Manual ARMv7-A and ARMv7-R edition, page 1687 */ 232 /* 233 * Control register bit values see ch. B4.1.130 of ARM Architecture Reference 234 * Manual ARMv7-A and ARMv7-R edition, page 1687 235 */ 229 236 enum { 230 237 SCTLR_MMU_EN_FLAG = 1 << 0, -
kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h
r4f8772d4 r904b1bc 66 66 uint64_t value; 67 67 struct { 68 uint64_t base : 51; /**<TSB base address, bits 63:13. */69 u nsigned split : 1; /**< Split vs. common TSB for 8K and 64K70 * pages. HelenOS uses only 8K pages71 * for user mappings, so we always set72 * this to 0.73 */68 /** TSB base address, bits 63:13. */ 69 uint64_t base : 51; 70 /** Split vs. common TSB for 8K and 64K pages. HelenOS uses 71 * only 8K pages for user mappings, so we always set this to 0. 72 */ 73 unsigned split : 1; 74 74 unsigned : 9; 75 unsigned size : 3; /**< TSB size. Number of entries is76 * 512 * 2^size. */75 /** TSB size. Number of entries is 512 * 2^size. */ 76 unsigned size : 3; 77 77 } __attribute__((packed)); 78 78 } tsb_base_reg_t; -
kernel/arch/sparc64/include/arch/sun4u/cpu.h
r4f8772d4 r904b1bc 62 62 63 63 typedef struct { 64 uint32_t mid; /**< Processor ID as read from65 UPA_CONFIG/FIREPLANE_CONFIG. */64 /** Processor ID as read from UPA_CONFIG/FIREPLANE_CONFIG. */ 65 uint32_t mid; 66 66 ver_reg_t ver; 67 uint32_t clock_frequency; /**< Processor frequency in Hz. */ 68 uint64_t next_tick_cmpr; /**< Next clock interrupt should be 69 generated when the TICK register 70 matches this value. */ 67 /** Processor frequency in Hz. */ 68 uint32_t clock_frequency; 69 /** Next clock interrupt should be generated when the TICK register 70 * matches this value. 71 */ 72 uint64_t next_tick_cmpr; 71 73 } cpu_arch_t; 72 74 -
kernel/arch/sparc64/include/arch/sun4v/cpu.h
r4f8772d4 r904b1bc 59 59 60 60 typedef struct cpu_arch { 61 uint64_t id; /**< virtual processor ID */ 62 uint32_t clock_frequency; /**< Processor frequency in Hz. */ 63 uint64_t next_tick_cmpr; /**< Next clock interrupt should be 64 generated when the TICK register 65 matches this value. */ 66 exec_unit_t *exec_unit; /**< Physical core. */ 67 unsigned long proposed_nrdy; /**< Proposed No. of ready threads 68 so that cores are equally balanced. */ 61 /** Virtual processor ID */ 62 uint64_t id; 63 /** Processor frequency in Hz */ 64 uint32_t clock_frequency; 65 /** Next clock interrupt should be generated when the TICK register 66 * matches this value. 67 */ 68 uint64_t next_tick_cmpr; 69 /** Physical core. */ 70 exec_unit_t *exec_unit; 71 /** Proposed No. of ready threads so that cores are equally balanced. */ 72 unsigned long proposed_nrdy; 69 73 } cpu_arch_t; 70 74 -
kernel/arch/sparc64/src/mm/sun4u/tsb.c
r4f8772d4 r904b1bc 97 97 */ 98 98 99 tte->tag.invalid = true; /* invalidate the entry 100 * (tag target has this 101 * set to 0) */ 99 /* Invalidate the entry (tag target has this set to 0) */ 100 tte->tag.invalid = true; 102 101 103 102 write_barrier(); … … 142 141 */ 143 142 144 tte->tag.invalid = true; /* invalidate the entry 145 * (tag target has this 146 * set to 0) */ 143 /* Invalidate the entry (tag target has this set to 0) */ 144 tte->tag.invalid = true; 147 145 148 146 write_barrier(); -
kernel/arch/sparc64/src/sun4v/md.c
r4f8772d4 r904b1bc 66 66 /** machine description element (in the node block) */ 67 67 typedef struct { 68 uint8_t tag; /**< Type of element */ 69 uint8_t name_len; /**< Length in bytes of element name */ 70 uint16_t _reserved_field; /**< reserved field (zeros) */ 71 uint32_t name_offset; /**< Location offset of name associated 72 with this element relative to 73 start of name block */ 68 /** Type of element */ 69 uint8_t tag; 70 /** Length in bytes of element name */ 71 uint8_t name_len; 72 /** Reserved field (zeros) */ 73 uint16_t _reserved_field; 74 /** Location offset of name associated with this element relative to 75 * start of name block 76 */ 77 uint32_t name_offset; 78 74 79 union { 75 80 /** for elements of type “PROP_STR” and of type “PROP_DATA” */ -
kernel/doc/doxygroups.h
r4f8772d4 r904b1bc 1 1 2 2 /* Definitions of modules and its relations for generating Doxygen documentation */ 3 4 /** @defgroup kernel Kernel 5 */ 3 6 4 7 /** @defgroup genericadt Data types … … 14 17 */ 15 18 16 /** 17 * @defgroup time Time management 18 * @ingroup kernel 19 */ 20 21 /** 22 * @defgroup proc Scheduling 23 * @ingroup kernel 24 */ 25 26 /** @defgroup genericproc generic 27 * @ingroup proc 28 */ 29 30 31 /** 32 * @cond amd64 33 * @defgroup amd64proc amd64 34 * @ingroup proc 35 * @endcond 36 */ 37 38 /** 39 * @cond arm32 40 * @defgroup arm32proc arm32 41 * @ingroup proc 42 * @endcond 43 */ 44 45 /** 46 * @cond ia32 47 * @defgroup ia32proc ia32 48 * @ingroup proc 49 * @endcond 50 */ 51 52 /** 53 * @cond ia64 54 * @defgroup ia64proc ia64 55 * @ingroup proc 56 * @endcond 57 */ 58 59 /** 60 * @cond mips32 61 * @defgroup mips32proc mips32 62 * @ingroup proc 63 * @endcond 64 */ 65 66 /** 67 * @cond ppc32 68 * @defgroup ppc32proc ppc32 69 * @ingroup proc 70 * @endcond 71 */ 72 73 /** 74 * @cond ppc64 75 * @defgroup ppc64proc ppc64 76 * @ingroup proc 77 * @endcond 78 */ 79 80 /** 81 * @cond sparc64 82 * @defgroup sparc64proc sparc64 83 * @ingroup proc 84 * @endcond 85 */ 19 /** @defgroup time Time management 20 * @ingroup kernel 21 */ 22 23 /** @defgroup proc Scheduling 24 * @ingroup kernel 25 */ 26 27 /** @defgroup genericproc generic 28 * @ingroup proc 29 */ 30 31 32 /** 33 * @cond amd64 34 * @defgroup amd64proc amd64 35 * @ingroup proc 36 * @endcond 37 */ 38 39 /** 40 * @cond arm32 41 * @defgroup arm32proc arm32 42 * @ingroup proc 43 * @endcond 44 */ 45 46 /** 47 * @cond ia32 48 * @defgroup ia32proc ia32 49 * @ingroup proc 50 * @endcond 51 */ 52 53 /** 54 * @cond ia64 55 * @defgroup ia64proc ia64 56 * @ingroup proc 57 * @endcond 58 */ 59 60 /** 61 * @cond mips32 62 * @defgroup mips32proc mips32 63 * @ingroup proc 64 * @endcond 65 */ 66 67 /** 68 * @cond ppc32 69 * @defgroup ppc32proc ppc32 70 * @ingroup proc 71 * @endcond 72 */ 73 74 /** 75 * @cond ppc64 76 * @defgroup ppc64proc ppc64 77 * @ingroup proc 78 * @endcond 79 */ 80 81 /** 82 * @cond sparc64 83 * @defgroup sparc64proc sparc64 84 * @ingroup proc 85 * @endcond 86 */ 86 87 87 88 … … 91 92 92 93 93 94 95 96 97 98 *@defgroup genericmm generic99 *@ingroup mm100 101 102 103 *@defgroup genarchmm genarch104 *@ingroup mm105 106 107 108 *@cond amd64109 *@defgroup amd64mm amd64110 *@ingroup mm111 *@endcond112 113 114 115 *@cond arm32116 *@defgroup arm32mm arm32117 *@ingroup mm118 *@endcond119 120 121 122 *@cond ia32123 *@defgroup ia32mm ia32124 *@ingroup mm125 *@endcond126 127 128 129 *@cond ia64130 *@defgroup ia64mm ia64131 *@ingroup mm132 *@endcond133 134 135 136 *@cond mips32137 *@defgroup mips32mm mips32138 *@ingroup mm139 *@endcond140 141 142 143 *@cond ppc32144 *@defgroup ppc32mm ppc32145 *@ingroup mm146 *@endcond147 148 149 150 *@cond ppc64151 *@defgroup ppc64mm ppc64152 *@ingroup mm153 *@endcond154 155 156 157 *@cond sparc64158 *@defgroup sparc64mm sparc64159 *@ingroup mm160 *@endcond161 94 /** @defgroup mm Memory management 95 * @ingroup kernel 96 */ 97 98 /** 99 * @defgroup genericmm generic 100 * @ingroup mm 101 */ 102 103 /** 104 * @defgroup genarchmm genarch 105 * @ingroup mm 106 */ 107 108 /** 109 * @cond amd64 110 * @defgroup amd64mm amd64 111 * @ingroup mm 112 * @endcond 113 */ 114 115 /** 116 * @cond arm32 117 * @defgroup arm32mm arm32 118 * @ingroup mm 119 * @endcond 120 */ 121 122 /** 123 * @cond ia32 124 * @defgroup ia32mm ia32 125 * @ingroup mm 126 * @endcond 127 */ 128 129 /** 130 * @cond ia64 131 * @defgroup ia64mm ia64 132 * @ingroup mm 133 * @endcond 134 */ 135 136 /** 137 * @cond mips32 138 * @defgroup mips32mm mips32 139 * @ingroup mm 140 * @endcond 141 */ 142 143 /** 144 * @cond ppc32 145 * @defgroup ppc32mm ppc32 146 * @ingroup mm 147 * @endcond 148 */ 149 150 /** 151 * @cond ppc64 152 * @defgroup ppc64mm ppc64 153 * @ingroup mm 154 * @endcond 155 */ 156 157 /** 158 * @cond sparc64 159 * @defgroup sparc64mm sparc64 160 * @ingroup mm 161 * @endcond 162 */ 162 163 163 164 … … 177 178 */ 178 179 179 /** @defgroup genericddi generic 180 * @ingroup ddi 181 */ 182 183 /** 184 * @cond amd64 185 * @defgroup amd64ddi amd64 186 * @ingroup ddi 187 * @endcond 188 */ 189 190 /** 191 * @cond arm32 192 * @defgroup arm32ddi arm32 193 * @ingroup ddi 194 * @endcond 195 */ 196 197 /** 198 * @cond ia32 199 * @defgroup ia32ddi ia32 200 * @ingroup ddi 201 * @endcond 202 */ 203 204 /** 205 * @cond ia64 206 * @defgroup ia64ddi ia64 207 * @ingroup ddi 208 * @endcond 209 */ 210 211 /** 212 * @cond mips32 213 * @defgroup mips32ddi mips32 214 * @ingroup ddi 215 * @endcond 216 */ 217 218 /** 219 * @cond ppc32 220 * @defgroup ppc32ddi ppc32 221 * @ingroup ddi 222 * @endcond 223 */ 224 225 /** 226 * @cond ppc64 227 * @defgroup ppc64ddi ppc64 228 * @ingroup ddi 229 * @endcond 230 */ 231 232 /** 233 * @cond sparc64 234 * @defgroup sparc64ddi sparc64 235 * @ingroup ddi 236 * @endcond 237 */ 238 239 /** @defgroup debug Debugging 180 /** 181 * @defgroup genericddi generic 182 * @ingroup ddi 183 */ 184 185 /** 186 * @cond amd64 187 * @defgroup amd64ddi amd64 188 * @ingroup ddi 189 * @endcond 190 */ 191 192 /** 193 * @cond arm32 194 * @defgroup arm32ddi arm32 195 * @ingroup ddi 196 * @endcond 197 */ 198 199 /** 200 * @cond ia32 201 * @defgroup ia32ddi ia32 202 * @ingroup ddi 203 * @endcond 204 */ 205 206 /** 207 * @cond ia64 208 * @defgroup ia64ddi ia64 209 * @ingroup ddi 210 * @endcond 211 */ 212 213 /** 214 * @cond mips32 215 * @defgroup mips32ddi mips32 216 * @ingroup ddi 217 * @endcond 218 */ 219 220 /** 221 * @cond ppc32 222 * @defgroup ppc32ddi ppc32 223 * @ingroup ddi 224 * @endcond 225 */ 226 227 /** 228 * @cond ppc64 229 * @defgroup ppc64ddi ppc64 230 * @ingroup ddi 231 * @endcond 232 */ 233 234 /** 235 * @cond sparc64 236 * @defgroup sparc64ddi sparc64 237 * @ingroup ddi 238 * @endcond 239 */ 240 241 /** @defgroup debug Debugging 240 242 * @ingroup others 241 243 */ 242 244 243 /** @defgroup genericdebug generic 244 * @ingroup debug 245 */ 246 247 /** 248 * @cond amd64 249 * @defgroup amd64debug ia32/amd64 250 * @ingroup debug 251 * @endcond 252 */ 253 254 /** 255 * @cond arm32 256 * @defgroup arm32debug arm32 257 * @ingroup debug 258 * @endcond 259 */ 260 261 /** 262 * @cond ia32 263 * @defgroup amd64debug ia32/amd64 264 * @ingroup debug 265 * @endcond 266 */ 267 268 /** 269 * @cond ia64 270 * @defgroup ia64debug ia64 271 * @ingroup debug 272 * @endcond 273 */ 274 275 /** 276 * @cond mips32 277 * @defgroup mips32debug mips32 278 * @ingroup debug 279 * @endcond 280 */ 281 282 /** 283 * @cond ppc32 284 * @defgroup ppc32debug ppc32 285 * @ingroup debug 286 * @endcond 287 */ 288 289 /** 290 * @cond ppc64 291 * @defgroup ppc64debug ppc64 292 * @ingroup debug 293 * @endcond 294 */ 295 296 /** 297 * @cond sparc64 298 * @defgroup sparc64debug sparc64 299 * @ingroup debug 300 * @endcond 301 */ 302 303 /** @defgroup interrupt Interrupt handling and dispatching 304 * @ingroup kernel 305 */ 306 /** 307 * @defgroup genericinterrupt generic 308 * @ingroup interrupt 309 */ 310 311 /** 312 * @cond amd64 313 * @defgroup amd64interrupt amd64 314 * @ingroup interrupt 315 * @endcond 316 */ 317 318 /** 319 * @cond arm32 320 * @defgroup arm32interrupt arm32 321 * @ingroup interrupt 322 * @endcond 323 */ 324 325 /** 326 * @cond ia32 327 * @defgroup ia32interrupt ia32 328 * @ingroup interrupt 329 * @endcond 330 */ 331 332 /** 333 * @cond ia64 334 * @defgroup ia64interrupt ia64 335 * @ingroup interrupt 336 * @endcond 337 */ 338 339 /** 340 * @cond mips32 341 * @defgroup mips32interrupt mips32 342 * @ingroup interrupt 343 * @endcond 344 */ 345 346 /** 347 * @cond ppc32 348 * @defgroup ppc32interrupt ppc32 349 * @ingroup interrupt 350 * @endcond 351 */ 352 353 /** 354 * @cond ppc64 355 * @defgroup ppc64interrupt ppc64 356 * @ingroup interrupt 357 * @endcond 358 */ 359 360 /** 361 * @cond sparc64 362 * @defgroup sparc64interrupt sparc64 363 * @ingroup interrupt 364 * @endcond 365 */ 245 /** 246 * @defgroup genericdebug generic 247 * @ingroup debug 248 */ 249 250 /** 251 * @cond amd64 252 * @defgroup amd64debug ia32/amd64 253 * @ingroup debug 254 * @endcond 255 */ 256 257 /** 258 * @cond arm32 259 * @defgroup arm32debug arm32 260 * @ingroup debug 261 * @endcond 262 */ 263 264 /** 265 * @cond ia32 266 * @defgroup amd64debug ia32/amd64 267 * @ingroup debug 268 * @endcond 269 */ 270 271 /** 272 * @cond ia64 273 * @defgroup ia64debug ia64 274 * @ingroup debug 275 * @endcond 276 */ 277 278 /** 279 * @cond mips32 280 * @defgroup mips32debug mips32 281 * @ingroup debug 282 * @endcond 283 */ 284 285 /** 286 * @cond ppc32 287 * @defgroup ppc32debug ppc32 288 * @ingroup debug 289 * @endcond 290 */ 291 292 /** 293 * @cond ppc64 294 * @defgroup ppc64debug ppc64 295 * @ingroup debug 296 * @endcond 297 */ 298 299 /** 300 * @cond sparc64 301 * @defgroup sparc64debug sparc64 302 * @ingroup debug 303 * @endcond 304 */ 305 306 /** @defgroup interrupt Interrupt handling and dispatching 307 * @ingroup kernel 308 */ 309 /** 310 * @defgroup genericinterrupt generic 311 * @ingroup interrupt 312 */ 313 314 /** 315 * @cond amd64 316 * @defgroup amd64interrupt amd64 317 * @ingroup interrupt 318 * @endcond 319 */ 320 321 /** 322 * @cond arm32 323 * @defgroup arm32interrupt arm32 324 * @ingroup interrupt 325 * @endcond 326 */ 327 328 /** 329 * @cond ia32 330 * @defgroup ia32interrupt ia32 331 * @ingroup interrupt 332 * @endcond 333 */ 334 335 /** 336 * @cond ia64 337 * @defgroup ia64interrupt ia64 338 * @ingroup interrupt 339 * @endcond 340 */ 341 342 /** 343 * @cond mips32 344 * @defgroup mips32interrupt mips32 345 * @ingroup interrupt 346 * @endcond 347 */ 348 349 /** 350 * @cond ppc32 351 * @defgroup ppc32interrupt ppc32 352 * @ingroup interrupt 353 * @endcond 354 */ 355 356 /** 357 * @cond ppc64 358 * @defgroup ppc64interrupt ppc64 359 * @ingroup interrupt 360 * @endcond 361 */ 362 363 /** 364 * @cond sparc64 365 * @defgroup sparc64interrupt sparc64 366 * @ingroup interrupt 367 * @endcond 368 */ 366 369 367 370 … … 369 372 * @ingroup kernel 370 373 */ 371 /** @defgroup generic generic 372 * @ingroup others 373 */ 374 375 /** @defgroup genarch genarch 376 * @ingroup others 377 */ 378 379 /** 380 * @cond amd64 381 * @defgroup amd64 amd64 382 * @ingroup others 383 * @endcond 384 */ 385 386 /** 387 * @cond arm32 388 * @defgroup arm32 arm32 389 * @ingroup others 390 * @endcond 391 */ 392 393 /** 394 * @cond ia32 395 * @defgroup ia32 ia32 396 * @ingroup others 397 * @endcond 398 */ 399 400 /** 401 * @cond ia64 402 * @defgroup ia64 ia64 403 * @ingroup others 404 * @endcond 405 */ 406 407 /** 408 * @cond mips32 409 * @defgroup mips32 mips32 410 * @ingroup others 411 * @endcond 412 */ 413 414 /** 415 * @cond ppc32 416 * @defgroup ppc32 ppc32 417 * @ingroup others 418 * @endcond 419 */ 420 421 /** 422 * @cond ppc64 423 * @defgroup ppc64 ppc64 424 * @ingroup others 425 * @endcond 426 */ 427 428 /** 429 * @cond sparc64 430 * @defgroup sparc64 sparc64 431 * @ingroup others 432 * @endcond 433 */ 374 375 /** 376 * @defgroup generic generic 377 * @ingroup others 378 */ 379 380 /** 381 * @defgroup genarch genarch 382 * @ingroup others 383 */ 384 385 /** 386 * @cond amd64 387 * @defgroup amd64 amd64 388 * @ingroup others 389 * @endcond 390 */ 391 392 /** 393 * @cond arm32 394 * @defgroup arm32 arm32 395 * @ingroup others 396 * @endcond 397 */ 398 399 /** 400 * @cond ia32 401 * @defgroup ia32 ia32 402 * @ingroup others 403 * @endcond 404 */ 405 406 /** 407 * @cond ia64 408 * @defgroup ia64 ia64 409 * @ingroup others 410 * @endcond 411 */ 412 413 /** 414 * @cond mips32 415 * @defgroup mips32 mips32 416 * @ingroup others 417 * @endcond 418 */ 419 420 /** 421 * @cond ppc32 422 * @defgroup ppc32 ppc32 423 * @ingroup others 424 * @endcond 425 */ 426 427 /** 428 * @cond ppc64 429 * @defgroup ppc64 ppc64 430 * @ingroup others 431 * @endcond 432 */ 433 434 /** 435 * @cond sparc64 436 * @defgroup sparc64 sparc64 437 * @ingroup others 438 * @endcond 439 */ -
kernel/genarch/include/genarch/drivers/omap/irc.h
r4f8772d4 r904b1bc 50 50 const uint8_t padd0[12]; 51 51 52 /* This register controls the various parameters 52 /* 53 * This register controls the various parameters 53 54 * of the OCP interface. 54 55 */ … … 78 79 #define OMAP_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) 79 80 80 /* This register controls protection of the other registers. 81 /* 82 * This register controls protection of the other registers. 81 83 * This register can only be accessed in priviledged mode, regardless 82 84 * of the current value of the protection bit. … … 85 87 #define OMAP_IRC_PROTECTION_FLAG (1 << 0) 86 88 87 /* This register controls the clock auto-idle for the functional 89 /* 90 * This register controls the clock auto-idle for the functional 88 91 * clock and the input synchronizers. 89 92 */ … … 119 122 ioport32_t mir; 120 123 121 /* This register is used to clear the interrupt mask bits, 124 /* 125 * This register is used to clear the interrupt mask bits, 122 126 * Write 1 clears the mask bit to 0. 123 127 */ 124 128 ioport32_t mir_clear; 125 129 126 /* This register is used to set the interrupt mask bits, 130 /* 131 * This register is used to set the interrupt mask bits, 127 132 * Write 1 sets the mask bit to 1. 128 133 */ 129 134 ioport32_t mir_set; 130 135 131 /* This register is used to set the software interrupt bits, 136 /* 137 * This register is used to set the software interrupt bits, 132 138 * it is also used to read the current active software 133 139 * interrupts. … … 136 142 ioport32_t isr_set; 137 143 138 /* This register is used to clear the software interrups bits. 144 /* 145 * This register is used to clear the software interrups bits. 139 146 * Write 1 clears the software interrupt bits to 0. 140 147 */ … … 150 157 const uint32_t padd4[8 * OMAP_IRC_IRQ_GROUPS_PAD]; 151 158 152 /* These registers contain the priority for the interrups and 159 /* 160 * These registers contain the priority for the interrups and 153 161 * the FIQ/IRQ steering. 154 162 */ 155 163 ioport32_t ilr[OMAP_IRC_IRQ_COUNT]; 164 165 } omap_irc_regs_t; 166 156 167 /* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */ 157 168 #define OMAP_IRC_ILR_FIQNIRQ_FLAG (1 << 0) … … 159 170 #define OMAP_IRC_ILR_PRIORITY_SHIFT 2 160 171 161 } omap_irc_regs_t;162 163 172 static inline void omap_irc_init(omap_irc_regs_t *regs) 164 173 { … … 167 176 /* Initialization sequence */ 168 177 169 /* 1 - Program the SYSCONFIG register: if necessary, enable the 178 /* 179 * 1 - Program the SYSCONFIG register: if necessary, enable the 170 180 * autogating by setting the AUTOIDLE bit. 171 181 */ 172 182 regs->sysconfig &= ~OMAP_IRC_SYSCONFIG_AUTOIDLE_FLAG; 173 183 174 /* 2 - Program the IDLE register: if necessary, disable functional 184 /* 185 * 2 - Program the IDLE register: if necessary, disable functional 175 186 * clock autogating or enable synchronizer autogating by setting 176 187 * the FUNCIDLE bit or the TURBO bit accordingly. … … 179 190 regs->idle &= ~OMAP_IRC_IDLE_TURBO_FLAG; 180 191 181 /* 3 - Program ILRm register for each interrupt line: Assign a 192 /* 193 * 3 - Program ILRm register for each interrupt line: Assign a 182 194 * priority level and set the FIQNIRQ bit for an FIQ interrupt 183 195 * (by default, interrupts are mapped to IRQ and … … 188 200 regs->ilr[i] = 0; 189 201 190 /* 4 - Program the MIRn register: Enable interrupts (by default, 202 /* 203 * 4 - Program the MIRn register: Enable interrupts (by default, 191 204 * all interrupt lines are masked). 192 205 */ -
kernel/generic/include/ddi/ddi.h
r4f8772d4 r904b1bc 43 43 /** Structure representing contiguous physical memory area. */ 44 44 typedef struct { 45 link_t link; /**< Linked list link */ 45 /** Linked list link */ 46 link_t link; 46 47 47 uintptr_t pbase; /**< Physical base of the area. */ 48 pfn_t frames; /**< Number of frames in the area. */ 49 bool unpriv; /**< Allow mapping by unprivileged tasks. */ 50 bool mapped; /**< Indicate whether the area is actually 51 mapped. */ 48 /** Physical base of the area. */ 49 uintptr_t pbase; 50 /** Number of frames in the area. */ 51 pfn_t frames; 52 /** Allow mapping by unprivileged tasks. */ 53 bool unpriv; 54 /** Indicate whether the area is actually mapped. */ 55 bool mapped; 52 56 } parea_t; 53 57
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