Changeset 6ff23ff in mainline for kernel


Ignore:
Timestamp:
2018-05-17T13:46:56Z (7 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
4f8772d4
Parents:
7c3fb9b
git-author:
Jiri Svoboda <jiri@…> (2018-05-16 18:44:36)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-17 13:46:56)
Message:

More comment fixing (ccheck).

Location:
kernel
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/arch/barrier.h

    r7c3fb9b r6ff23ff  
    4949
    5050#if defined PROCESSOR_ARCH_armv7_a
    51 /* ARMv7 uses instructions for memory barriers see ARM Architecture reference
     51/*
     52 * ARMv7 uses instructions for memory barriers see ARM Architecture reference
    5253 * manual for details:
    5354 * DMB: ch. A8.8.43 page A8-376
    … …  
    6970 * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
    7071 */
    71 /* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
     72/*
     73 * ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
    7274 * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
    7375 * CP15 implementation is mandatory only for armv6+.
    … …  
    8688#endif
    8789#else
    88 /* Older manuals mention syscalls as a way to implement cache coherency and
     90/*
     91 * Older manuals mention syscalls as a way to implement cache coherency and
    8992 * barriers. See for example ARM Architecture Reference Manual Version D
    9093 * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
    … …  
    123126        inst_barrier();                /* Wait for Inst refetch */\
    124127} while (0)
    125 /* @note: Cache type register is not available in uspace. We would need
    126  * to export the cache line value, or use syscall for uspace smc_coherence */
     128/*
     129 * @note: Cache type register is not available in uspace. We would need
     130 * to export the cache line value, or use syscall for uspace smc_coherence
     131 */
    127132#define smc_coherence_block(a, l) \
    128133do { \

  • kernel/arch/arm32/src/fpu_context.c

    r7c3fb9b r6ff23ff  
    117117static int fpu_have_coprocessor_access(void)
    118118{
    119 /*
    120  * The register containing the information (CPACR) is not available on armv6-
    121  * rely on user decision to use CONFIG_FPU.
    122  */
     119        /*
     120         * The register containing the information (CPACR) is not available
     121         * on armv6-. Rely on user decision to use CONFIG_FPU.
     122        */
    123123#ifdef PROCESSOR_ARCH_armv7_a
    124124        const uint32_t cpacr = CPACR_read();
    125         /* FPU needs access to coprocessor 10 and 11.
    126          * Moreover they need to have same access enabled */
     125        /*
     126         * FPU needs access to coprocessor 10 and 11.
     127         * Moreover, they need to have same access enabled
     128         */
    127129        if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
    128130            ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
    … …  
    131133        }
    132134#endif
     135
    133136        return 1;
    134137}
    … …  
    147150static void fpu_enable_coprocessor_access(void)
    148151{
    149 /*
    150  * The register containing the information (CPACR) is not available on armv6-
    151  * rely on user decision to use CONFIG_FPU.
    152  */
     152        /*
     153         * The register containing the information (CPACR) is not available
     154         * on armv6-. Rely on user decision to use CONFIG_FPU.
     155        */
    153156#ifdef PROCESSOR_ARCH_armv7_a
    154157        /* Allow coprocessor access */
    155158        uint32_t cpacr = CPACR_read();
    156         /* FPU needs access to coprocessor 10 and 11.
    157          * Moreover, they need to have same access enabled */
     159        /*
     160         * FPU needs access to coprocessor 10 and 11.
     161         * Moreover, they need to have same access enabled
     162         */
    158163        cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
    159164        cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
    … …  
    172177        fpexc_write(0);
    173178        fpu_enable();
    174         /* Mask all exception traps,
     179        /*
     180         * Mask all exception traps,
    175181         * The bits are RAZ/WI on archs that don't support fpu exc traps.
    176182         */

  • kernel/generic/src/ipc/sysipc.c

    r7c3fb9b r6ff23ff  
    119119
    120120
    121 /***********************************************************************
     121/*
    122122 * Functions that preprocess answer before sending it to the recepient.
    123  ***********************************************************************/
     123 */
    124124
    125125/** Decide if the caller (e.g. ipc_answer()) should save the old call contents
    … …  
    228228}
    229229
    230 /*******************************************************************************
     230/*
    231231 * Functions called to process received call/answer before passing it to uspace.
    232  *******************************************************************************/
     232 */
    233233
    234234/** Do basic kernel processing of received call answer.

  • kernel/generic/src/printf/printf_core.c

    r7c3fb9b r6ff23ff  
    784784
    785785                        switch (uc) {
    786                         /*
    787                         * String and character conversions.
    788                         */
     786                                /*
     787                                * String and character conversions.
     788                                */
    789789                        case 's':
    790790                                if (qualifier == PrintfQualifierLong)
    … …  
    816816                                continue;
    817817
    818                         /*
    819                         * Integer values
    820                         */
     818                                /*
     819                                * Integer values
     820                                */
    821821                        case 'P':
    822822                                /* Pointer */
    … …  
    848848                                break;
    849849
    850                         /* Percentile itself */
    851850                        case '%':
     851                                /* Percentile itself */
    852852                                j = i;
    853853                                continue;
    854854
    855                         /*
    856                         * Bad formatting.
    857                         */
     855                                /*
     856                                * Bad formatting.
     857                                */
    858858                        default:
    859859                                /*

  • kernel/generic/src/udebug/udebug_ipc.c

    r7c3fb9b r6ff23ff  
    5454{
    5555        switch (IPC_GET_ARG1(call->data)) {
    56         /* future UDEBUG_M_REGS_WRITE, UDEBUG_M_MEM_WRITE: */
     56                /* future UDEBUG_M_REGS_WRITE, UDEBUG_M_MEM_WRITE: */
    5757        default:
    5858                break;
    … …  
    193193
    194194        IPC_SET_RETVAL(call->data, 0);
    195         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    196            same code in process_answer() can be used
    197            (no way to distinguish method in answer) */
     195        /*
     196         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     197         * same code in process_answer() can be used
     198         * (no way to distinguish method in answer)
     199         */
    198200        IPC_SET_ARG1(call->data, uspace_addr);
    199201        IPC_SET_ARG2(call->data, copied);
    … …  
    238240
    239241        IPC_SET_RETVAL(call->data, 0);
    240         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    241            same code in process_answer() can be used
    242            (no way to distinguish method in answer) */
     242        /*
     243         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     244         * same code in process_answer() can be used
     245         * (no way to distinguish method in answer)
     246         */
    243247        IPC_SET_ARG1(call->data, uspace_addr);
    244248        IPC_SET_ARG2(call->data, to_copy);
    … …  
    285289
    286290        IPC_SET_RETVAL(call->data, 0);
    287         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    288            same code in process_answer() can be used
    289            (no way to distinguish method in answer) */
     291        /*
     292         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     293         * same code in process_answer() can be used
     294         * (no way to distinguish method in answer)
     295         */
    290296        IPC_SET_ARG1(call->data, uspace_addr);
    291297        IPC_SET_ARG2(call->data, to_copy);
    … …  
    326332
    327333        IPC_SET_RETVAL(call->data, 0);
    328         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    329            same code in process_answer() can be used
    330            (no way to distinguish method in answer) */
     334        /*
     335         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     336         * same code in process_answer() can be used
     337         * (no way to distinguish method in answer)
     338         */
    331339        IPC_SET_ARG1(call->data, uspace_addr);
    332340        IPC_SET_ARG2(call->data, 6 * sizeof(sysarg_t));
    … …  
    367375
    368376        IPC_SET_RETVAL(call->data, 0);
    369         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    370            same code in process_answer() can be used
    371            (no way to distinguish method in answer) */
     377        /*
     378         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     379         * same code in process_answer() can be used
     380         * (no way to distinguish method in answer)
     381         */
    372382        IPC_SET_ARG1(call->data, uspace_addr);
    373383        IPC_SET_ARG2(call->data, to_copy);
    … …  
    406416
    407417        IPC_SET_RETVAL(call->data, 0);
    408         /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
    409            same code in process_answer() can be used
    410            (no way to distinguish method in answer) */
     418        /*
     419         * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that
     420         * same code in process_answer() can be used
     421         * (no way to distinguish method in answer)
     422         */
    411423        IPC_SET_ARG1(call->data, uspace_dst);
    412424        IPC_SET_ARG2(call->data, size);
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