Changeset 8c5e6c7 in mainline for arch/mips32/src/mm/tlb.c

Timestamp:

2005-10-07T23:19:56Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

cad5ce8

Parents:

92e5431

Message:

mips32 memory management work.
TLB exceptions seem to be working on at least simics.
msim handles TLB Refill and TLB Invalid exceptions well,
but seems to skip writes to the mapped addressies in mm
mapping test #1 (the data is not written and exception
is not triggered).

File:

• arch/mips32/src/mm/tlb.c (modified) (10 diffs)

arch/mips32/src/mm/tlb.c

@@ -45 +45 @@
 
 static pte_t *find_mapping_and_check(__address badvaddr);
+
 static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
+static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
 
 /** Initialize TLB
@@ -85 +87 @@
 {
         entry_lo_t lo;
+        entry_hi_t hi;  
         __address badvaddr;
         pte_t *pte;
 
-// debug        
-        entry_hi_t hi;
-
         badvaddr = cp0_badvaddr_read();
 
-// debug
-        hi.value = cp0_entry_hi_read();
-        printf("TLB Refill: hi.vnp2=%X\n", hi.vpn2);
-        
         spinlock_lock(&VM->lock);               
+
         pte = find_mapping_and_check(badvaddr);
         if (!pte)
@@ -107 +104 @@
         pte->a = 1;
 
+        prepare_entry_hi(&hi, VM->asid, badvaddr);
         prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
 
@@ -112 +110 @@
          * New entry is to be inserted into TLB
          */
+        cp0_entry_hi_write(hi.value);
         if ((badvaddr/PAGE_SIZE) % 2 == 0) {
                 cp0_entry_lo0_write(lo.value);
@@ -141 +140 @@
         __address badvaddr;
         entry_lo_t lo;
+        entry_hi_t hi;
         pte_t *pte;
 
@@ -148 +148 @@
          * Locate the faulting entry in TLB.
          */
+        hi.value = cp0_entry_hi_read();
+        prepare_entry_hi(&hi, hi.asid, badvaddr);
+        cp0_entry_hi_write(hi.value);
         tlbp();
         index.value = cp0_index_read();
@@ -205 +208 @@
         __address badvaddr;
         entry_lo_t lo;
+        entry_hi_t hi;
         pte_t *pte;
 
@@ -212 +216 @@
          * Locate the faulting entry in TLB.
          */
+        hi.value = cp0_entry_hi_read();
+        prepare_entry_hi(&hi, hi.asid, badvaddr);
+        cp0_entry_hi_write(hi.value);
         tlbp();
         index.value = cp0_index_read();
@@ -379 +386 @@
 void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
 {
+        lo->value = 0;
         lo->g = g;
         lo->v = v;
@@ -384 +392 @@
         lo->c = c;
         lo->pfn = pfn;
-        lo->zero = 0;
-}
+}
+
+void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
+{
+        hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2);
+        hi->asid = asid;
+}