Changeset 8565a42 in mainline for kernel/arch/sparc64/src/mm/sun4u/as.c

Timestamp:

2018-03-02T20:34:50Z (7 years ago)

Author:

GitHub <noreply@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1a81f69, d5e5fd1

Parents:

3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)

git-committer:

GitHub <noreply@…> (2018-03-02 20:34:50)

Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:

• kernel/arch/sparc64/src/mm/sun4u/as.c (modified) (9 diffs)

kernel/arch/sparc64/src/mm/sun4u/as.c

@@ -69 +69 @@
         tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_base);
         memsetb(tsb, TSB_SIZE, 0);
-        
+
         as->arch.itsb = tsb;
         as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
 #endif
-        
+
         return EOK;
 }
@@ -81 +81 @@
 #ifdef CONFIG_TSB
         frame_free(KA2PA((uintptr_t) as->arch.itsb), TSB_FRAMES);
-        
+
         return TSB_FRAMES;
 #else
@@ -93 +93 @@
         tsb_invalidate(as, 0, (size_t) -1);
 #endif
-        
+
         return 0;
 }
@@ -107 +107 @@
 {
         tlb_context_reg_t ctx;
-        
+
         /*
          * Note that we don't and may not lock the address space. That's ok
@@ -115 +115 @@
          *
          */
-        
+
         /*
          * Write ASID to secondary context register. The primary context
@@ -126 +126 @@
         ctx.context = as->asid;
         mmu_secondary_context_write(ctx.v);
-        
+
 #ifdef CONFIG_TSB
         uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-        
+
         assert(as->arch.itsb);
         assert(as->arch.dtsb);
-        
+
         uintptr_t tsb = (uintptr_t) as->arch.itsb;
-        
+
         if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
                 /*
@@ -145 +145 @@
                 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
         }
-        
+
         /*
          * Setup TSB Base registers.
@@ -151 +151 @@
          */
         tsb_base_reg_t tsb_base_reg;
-        
+
         tsb_base_reg.value = 0;
         tsb_base_reg.size = TSB_BASE_REG_SIZE;
         tsb_base_reg.split = 0;
-        
+
         tsb_base_reg.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
         itsb_base_write(tsb_base_reg.value);
         tsb_base_reg.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
         dtsb_base_write(tsb_base_reg.value);
-        
+
 #if defined (US3)
         /*
@@ -198 +198 @@
          *
          */
-        
+
 #ifdef CONFIG_TSB
         uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-        
+
         assert(as->arch.itsb);
         assert(as->arch.dtsb);
-        
+
         uintptr_t tsb = (uintptr_t) as->arch.itsb;
-        
+
         if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
                 /*