Changeset 8565a42 in mainline for kernel/arch/ia32/src/smp/apic.c

Timestamp:

2018-03-02T20:34:50Z (8 years ago)

Author:

GitHub <noreply@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a1a81f69, d5e5fd1

Parents:

3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)

git-committer:

GitHub <noreply@…> (2018-03-02 20:34:50)

Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:

• kernel/arch/ia32/src/smp/apic.c (modified) (33 diffs)

kernel/arch/ia32/src/smp/apic.c

@@ -164 +164 @@
 {
         l_apic_id_t idreg;
-        
+
         idreg.value = l_apic[L_APIC_ID];
         return idreg.apic_id;
@@ -174 +174 @@
         exc_register(VECTOR_APIC_SPUR, "apic_spurious", false,
             (iroutine_t) apic_spurious);
-        
+
         enable_irqs_function = io_apic_enable_irqs;
         disable_irqs_function = io_apic_disable_irqs;
         eoi_function = l_apic_eoi;
         irqs_info = "apic";
-        
+
         /*
          * Configure interrupt routing.
@@ -186 +186 @@
          */
         io_apic_disable_irqs(0xffffU);
-        
+
         irq_initialize(&l_apic_timer_irq);
         l_apic_timer_irq.preack = true;
@@ -193 +193 @@
         l_apic_timer_irq.handler = l_apic_timer_irq_handler;
         irq_register(&l_apic_timer_irq);
-        
+
         uint8_t i;
         for (i = 0; i < IRQ_COUNT; i++) {
                 int pin;
-                
+
                 if ((pin = smp_irq_to_pin(i)) != -1)
                         io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI);
         }
-        
+
         /*
          * Ensure that io_apic has unique ID.
          */
         io_apic_id_t idreg;
-        
+
         idreg.value = io_apic_read(IOAPICID);
         if ((1 << idreg.apic_id) & apic_id_mask) {  /* See if IO APIC ID is used already */
@@ -217 +217 @@
                 }
         }
-        
+
         /*
          * Configure the BSP's lapic.
@@ -223 +223 @@
         l_apic_init();
         l_apic_debug();
-        
+
         bsp_l_apic = l_apic_id();
 }
@@ -237 +237 @@
 {
         esr_t esr;
-        
+
         esr.value = l_apic[ESR];
-        
+
         if (esr.err_bitmap) {
                 log_begin(LF_ARCH, LVL_ERROR);
@@ -259 +259 @@
                 log_end();
         }
-        
+
         return !esr.err_bitmap;
 }
@@ -267 +267 @@
 {
         icr_t icr;
-        
+
         do {
                 icr.lo = l_apic[ICRlo];
@@ -286 +286 @@
         /* Wait for a destination cpu to accept our previous ipi. */
         l_apic_wait_for_delivery();
-        
+
         icr.lo = l_apic[ICRlo];
         icr.hi = l_apic[ICRhi];
-        
+
         icr.delmod = DELMOD_FIXED;
         icr.destmod = DESTMOD_PHYS;
@@ -301 +301 @@
         l_apic[ICRhi] = icr.hi;
         l_apic[ICRlo] = icr.lo;
-        
+
         return apic_poll_errors();
 }
@@ -318 +318 @@
         /* Wait for a destination cpu to accept our previous ipi. */
         l_apic_wait_for_delivery();
-        
+
         icr.lo = l_apic[ICRlo];
         icr.delmod = DELMOD_FIXED;
@@ -326 +326 @@
         icr.trigger_mode = TRIGMOD_LEVEL;
         icr.vector = vector;
-        
+
         l_apic[ICRlo] = icr.lo;
-        
+
         return apic_poll_errors();
 }
@@ -345 +345 @@
          */
         icr_t icr;
-        
+
         icr.lo = l_apic[ICRlo];
         icr.hi = l_apic[ICRhi];
-        
+
         icr.delmod = DELMOD_INIT;
         icr.destmod = DESTMOD_PHYS;
@@ -356 +356 @@
         icr.vector = 0;
         icr.dest = apicid;
-        
+
         l_apic[ICRhi] = icr.hi;
         l_apic[ICRlo] = icr.lo;
-        
+
         /*
          * According to MP Specification, 20us should be enough to
@@ -365 +365 @@
          */
         delay(20);
-        
+
         if (!apic_poll_errors())
                 return 0;
-        
+
         l_apic_wait_for_delivery();
 
@@ -379 +379 @@
         icr.vector = 0;
         l_apic[ICRlo] = icr.lo;
-        
+
         /*
          * Wait 10ms as MP Specification specifies.
          */
         delay(10000);
-        
+
         if (!is_82489DX_apic(l_apic[LAVR])) {
                 /*
@@ -402 +402 @@
                 }
         }
-        
+
         return apic_poll_errors();
 }
@@ -411 +411 @@
         /* Initialize LVT Error register. */
         lvt_error_t error;
-        
+
         error.value = l_apic[LVT_Err];
         error.masked = true;
         l_apic[LVT_Err] = error.value;
-        
+
         /* Initialize LVT LINT0 register. */
         lvt_lint_t lint;
-        
+
         lint.value = l_apic[LVT_LINT0];
         lint.masked = true;
         l_apic[LVT_LINT0] = lint.value;
-        
+
         /* Initialize LVT LINT1 register. */
         lint.value = l_apic[LVT_LINT1];
         lint.masked = true;
         l_apic[LVT_LINT1] = lint.value;
-        
+
         /* Task Priority Register initialization. */
         tpr_t tpr;
-        
+
         tpr.value = l_apic[TPR];
         tpr.pri_sc = 0;
         tpr.pri = 0;
         l_apic[TPR] = tpr.value;
-        
+
         /* Spurious-Interrupt Vector Register initialization. */
         svr_t svr;
-        
+
         svr.value = l_apic[SVR];
         svr.vector = VECTOR_APIC_SPUR;
@@ -444 +444 @@
         svr.focus_checking = true;
         l_apic[SVR] = svr.value;
-        
+
         if (CPU->arch.family >= 6)
                 enable_l_apic_in_msr();
-        
+
         /* Interrupt Command Register initialization. */
         icr_t icr;
-        
+
         icr.lo = l_apic[ICRlo];
         icr.delmod = DELMOD_INIT;
@@ -458 +458 @@
         icr.trigger_mode = TRIGMOD_LEVEL;
         l_apic[ICRlo] = icr.lo;
-        
+
         /* Timer Divide Configuration Register initialization. */
         tdcr_t tdcr;
-        
+
         tdcr.value = l_apic[TDCR];
         tdcr.div_value = DIVIDE_1;
         l_apic[TDCR] = tdcr.value;
-        
+
         /* Program local timer. */
         lvt_tm_t tm;
-        
+
         tm.value = l_apic[LVT_Tm];
         tm.vector = VECTOR_CLK;
@@ -474 +474 @@
         tm.masked = false;
         l_apic[LVT_Tm] = tm.value;
-        
+
         /*
          * Measure and configure the timer to generate timer
@@ -481 +481 @@
         uint32_t t1 = l_apic[CCRT];
         l_apic[ICRT] = 0xffffffff;
-        
+
         while (l_apic[CCRT] == t1);
-        
+
         t1 = l_apic[CCRT];
         delay(1000000 / HZ);
         uint32_t t2 = l_apic[CCRT];
-        
+
         l_apic[ICRT] = t1 - t2;
-        
+
         /* Program Logical Destination Register. */
         assert(CPU->id < 8);
         ldr_t ldr;
-        
+
         ldr.value = l_apic[LDR];
         ldr.id = (uint8_t) (1 << CPU->id);
         l_apic[LDR] = ldr.value;
-        
+
         /* Program Destination Format Register for Flat mode. */
         dfr_t dfr;
-        
+
         dfr.value = l_apic[DFR];
         dfr.model = MODEL_FLAT;
@@ -519 +519 @@
         log_printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
             CPU->id, l_apic_id());
-        
+
         lvt_tm_t tm;
         tm.value = l_apic[LVT_Tm];
@@ -525 +525 @@
             tm.vector, delivs_str[tm.delivs], mask_str[tm.masked],
             tm_mode_str[tm.mode]);
-        
+
         lvt_lint_t lint;
         lint.value = l_apic[LVT_LINT0];
@@ -532 +532 @@
             intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
             mask_str[lint.masked]);
-        
+
         lint.value = l_apic[LVT_LINT1];
         log_printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
@@ -538 +538 @@
             intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
             mask_str[lint.masked]);
-        
+
         lvt_error_t error;
         error.value = l_apic[LVT_Err];
@@ -557 +557 @@
 {
         io_regsel_t regsel;
-        
+
         regsel.value = io_apic[IOREGSEL];
         regsel.reg_addr = address;
@@ -573 +573 @@
 {
         io_regsel_t regsel;
-        
+
         regsel.value = io_apic[IOREGSEL];
         regsel.reg_addr = address;
@@ -592 +592 @@
 {
         unsigned int dlvr;
-        
+
         if (flags & LOPRI)
                 dlvr = DELMOD_LOWPRI;
         else
                 dlvr = DELMOD_FIXED;
-        
+
         io_redirection_reg_t reg;
         reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
         reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1));
-        
+
         reg.dest = dest;
         reg.destmod = DESTMOD_LOGIC;
@@ -608 +608 @@
         reg.delmod = dlvr;
         reg.intvec = vec;
-        
+
         io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
         io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi);
@@ -630 +630 @@
                         if (pin != -1) {
                                 io_redirection_reg_t reg;
-                                
+
                                 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
                                 reg.masked = true;
                                 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
                         }
-                        
+
                 }
         }
@@ -657 +657 @@
                         if (pin != -1) {
                                 io_redirection_reg_t reg;
-                                
+
                                 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
                                 reg.masked = false;
                                 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
                         }
-                        
+
                 }
         }