Changeset 8565a42 in mainline for kernel/arch/ia32/src/ddi/ddi.c


Ignore:
Timestamp:
2018-03-02T20:34:50Z (7 years ago)
Author:
GitHub <noreply@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a1a81f69, d5e5fd1
Parents:
3061bc1 (diff), 34e1206 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
git-author:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:34:50)
git-committer:
GitHub <noreply@…> (2018-03-02 20:34:50)
Message:

Remove all trailing whitespace, everywhere.

See individual commit messages for details.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/src/ddi/ddi.c

    r3061bc1 r8565a42  
    5959        /* First, copy the I/O Permission Bitmap. */
    6060        irq_spinlock_lock(&TASK->lock, false);
    61        
     61
    6262        size_t ver = TASK->arch.iomapver;
    6363        size_t elements = TASK->arch.iomap.elements;
    64        
     64
    6565        if (elements > 0) {
    6666                assert(TASK->arch.iomap.bits);
    67                
     67
    6868                bitmap_t iomap;
    6969                bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
    7070                    CPU->arch.tss->iomap);
    7171                bitmap_copy(&iomap, &TASK->arch.iomap, elements);
    72                
     72
    7373                /*
    7474                 * Set the trailing bits in the last byte of the map to disable
     
    7777                bitmap_set_range(&iomap, elements,
    7878                    ALIGN_UP(elements, 8) - elements);
    79                
     79
    8080                /*
    8181                 * It is safe to set the trailing eight bits because of the
     
    8484                bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8);
    8585        }
    86        
     86
    8787        irq_spinlock_unlock(&TASK->lock, false);
    88        
     88
    8989        /*
    9090         * Second, adjust TSS segment limit.
     
    9393        ptr_16_32_t cpugdtr;
    9494        gdtr_store(&cpugdtr);
    95        
     95
    9696        descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
    9797        size_t size = bitmap_size(elements);
    9898        gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
    9999        gdtr_load(&cpugdtr);
    100        
     100
    101101        /*
    102102         * Before we load new TSS limit, the current TSS descriptor
     
    105105        gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
    106106        tr_load(GDT_SELECTOR(TSS_DES));
    107        
     107
    108108        /*
    109109         * Update the generation count so that faults caused by
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