Changeset 8486c07 in mainline for uspace/drv


Ignore:
Timestamp:
2012-07-21T14:01:12Z (13 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
eb3683a
Parents:
56c167c
Message:

IRQ pseudocode improvements

  • rename CMD_BTEST to CMD_AND (less cryptic)
  • implement CMD_LOAD to load a constant value into a scratch register
  • implement simple pseudocode static checker
  • slightly alter the semantics of several pseudocode commands (scratch[0] is a usable field, although not propagated to the IPC notification)
Location:
uspace/drv
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/usb/ohci/hc.c

    r56c167c r8486c07  
    2626 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    2727 */
     28
    2829/** @addtogroup drvusbohcihc
    2930 * @{
    … …  
    3233 * @brief OHCI Host controller driver routines
    3334 */
     35
    3436#include <errno.h>
    3537#include <str_error.h>
    … …  
    4951static const irq_pio_range_t ohci_pio_ranges[] = {
    5052        {
    51                 .base = 0,      /* filled later */
     53                .base = 0,
    5254                .size = sizeof(ohci_regs_t)
    5355        }
    … …  
    5557
    5658static const irq_cmd_t ohci_irq_commands[] = {
    57         { .cmd = CMD_PIO_READ_32, .dstarg = 1, .addr = NULL /* filled later */ },
    58         { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2, .value = 0 /* filled later */ },
    59         { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
    60         { .cmd = CMD_PIO_WRITE_A_32, .srcarg = 1, .addr = NULL /* filled later */ },
    61         { .cmd = CMD_ACCEPT },
     59        {
     60                .cmd = CMD_PIO_READ_32,
     61                .dstarg = 1,
     62                .addr = NULL
     63        },
     64        {
     65                .cmd = CMD_AND,
     66                .srcarg = 1,
     67                .dstarg = 2,
     68                .value = OHCI_USED_INTERRUPTS
     69        },
     70        {
     71                .cmd = CMD_PREDICATE,
     72                .srcarg = 2,
     73                .value = 2
     74        },
     75        {
     76                .cmd = CMD_PIO_WRITE_A_32,
     77                .srcarg = 1,
     78                .addr = NULL
     79        },
     80        {
     81                .cmd = CMD_ACCEPT
     82        }
    6283};
    6384
    … …  
    7697        return sizeof(ohci_pio_ranges) / sizeof(irq_pio_range_t);
    7798}
    78 
    7999
    80100/** Get number of commands used in IRQ code.
    … …  
    111131        ohci_regs_t *registers = (ohci_regs_t *) regs;
    112132        cmds[0].addr = (void *) &registers->interrupt_status;
    113         cmds[1].value = OHCI_USED_INTERRUPTS;
    114133        cmds[3].addr = (void *) &registers->interrupt_status;
    115134
    … …  
    445464                return;
    446465        }
     466
    447467        const unsigned hc_status = C_HCFS_GET(instance->registers->control);
    448468        /* Interrupt routing disabled && status != USB_RESET => BIOS active */

  • uspace/drv/bus/usb/uhci/hc.c

    r56c167c r8486c07  
    5050static const irq_pio_range_t uhci_irq_pio_ranges[] = {
    5151        {
    52                 .base = 0,      /* filled later */
     52                .base = 0,
    5353                .size = sizeof(uhci_regs_t)
    5454        }
    … …  
    5656
    5757static const irq_cmd_t uhci_irq_commands[] = {
    58         { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
    59         { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
    60           .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
    61         { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
    62         { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
    63         { .cmd = CMD_ACCEPT },
     58        {
     59                .cmd = CMD_PIO_READ_16,
     60                .dstarg = 1,
     61                .addr = NULL
     62        },
     63        {
     64                .cmd = CMD_AND,
     65                .srcarg = 1,
     66                .dstarg = 2,
     67                .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS
     68        },
     69        {
     70                .cmd = CMD_PREDICATE,
     71                .srcarg = 2,
     72                .value = 2
     73        },
     74        {
     75                .cmd = CMD_PIO_WRITE_A_16,
     76                .srcarg = 1,
     77                .addr = NULL
     78        },
     79        {
     80                .cmd = CMD_ACCEPT
     81        }
    6482};
    6583

  • uspace/drv/char/i8042/i8042.c

    r56c167c r8486c07  
    120120        },
    121121        {
    122                 .cmd = CMD_BTEST,
     122                .cmd = CMD_AND,
    123123                .value = i8042_OUTPUT_FULL,
    124124                .srcarg = 1,

  • uspace/drv/nic/ne2k/ne2k.c

    r56c167c r8486c07  
    8383        {
    8484                /* Mask supported interrupt causes */
    85                 .cmd = CMD_BTEST,
     85                .cmd = CMD_AND,
    8686                .value = (ISR_PRX | ISR_PTX | ISR_RXE | ISR_TXE | ISR_OVW |
    8787                    ISR_CNT | ISR_RDC),
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