source: mainline/uspace/drv/bus/usb/uhci/hc.c@ 76fbd9a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 76fbd9a was 76fbd9a, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

usb drivers: remove optical separators
  • Property mode set to 100644
File size: 15.4 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41
42#include "hc.h"
43#include "uhci_batch.h"
44
45#define UHCI_INTR_ALLOW_INTERRUPTS \
46 (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
47#define UHCI_STATUS_USED_INTERRUPTS \
48 (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)
49
50static const irq_pio_range_t uhci_irq_pio_ranges[] = {
51 {
52 .base = 0, /* filled later */
53 .size = sizeof(uhci_regs_t)
54 }
55};
56
57static const irq_cmd_t uhci_irq_commands[] = {
58 { .cmd = CMD_PIO_READ_16, .dstarg = 1, .addr = NULL/*filled later*/},
59 { .cmd = CMD_BTEST, .srcarg = 1, .dstarg = 2,
60 .value = UHCI_STATUS_USED_INTERRUPTS | UHCI_STATUS_NM_INTERRUPTS },
61 { .cmd = CMD_PREDICATE, .srcarg = 2, .value = 2 },
62 { .cmd = CMD_PIO_WRITE_A_16, .srcarg = 1, .addr = NULL/*filled later*/},
63 { .cmd = CMD_ACCEPT },
64};
65
66static void hc_init_hw(const hc_t *instance);
67static int hc_init_mem_structures(hc_t *instance);
68static int hc_init_transfer_lists(hc_t *instance);
69static int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
70
71static int hc_interrupt_emulator(void *arg);
72static int hc_debug_checker(void *arg);
73
74
75/** Get number of PIO ranges used in IRQ code.
76 * @return Number of ranges.
77 */
78size_t hc_irq_pio_range_count(void)
79{
80 return sizeof(uhci_irq_pio_ranges) / sizeof(irq_pio_range_t);
81}
82
83/** Get number of commands used in IRQ code.
84 * @return Number of commands.
85 */
86size_t hc_irq_cmd_count(void)
87{
88 return sizeof(uhci_irq_commands) / sizeof(irq_cmd_t);
89}
90
91/** Generate IRQ code.
92 * @param[out] ranges PIO ranges buffer.
93 * @param[in] ranges_size Size of the ranges buffer (bytes).
94 * @param[out] cmds Commands buffer.
95 * @param[in] cmds_size Size of the commands buffer (bytes).
96 * @param[in] regs Physical address of device's registers.
97 * @param[in] reg_size Size of the register area (bytes).
98 *
99 * @return Error code.
100 */
101int
102hc_get_irq_code(irq_pio_range_t ranges[], size_t ranges_size, irq_cmd_t cmds[],
103 size_t cmds_size, uintptr_t regs, size_t reg_size)
104{
105 if ((ranges_size < sizeof(uhci_irq_pio_ranges)) ||
106 (cmds_size < sizeof(uhci_irq_commands)) ||
107 (reg_size < sizeof(uhci_regs_t)))
108 return EOVERFLOW;
109
110 memcpy(ranges, uhci_irq_pio_ranges, sizeof(uhci_irq_pio_ranges));
111 ranges[0].base = regs;
112
113 memcpy(cmds, uhci_irq_commands, sizeof(uhci_irq_commands));
114 uhci_regs_t *registers = (uhci_regs_t *) regs;
115 cmds[0].addr = &registers->usbsts;
116 cmds[3].addr = &registers->usbsts;
117
118 return EOK;
119}
120
121/** Take action based on the interrupt cause.
122 *
123 * @param[in] instance UHCI structure to use.
124 * @param[in] status Value of the status register at the time of interrupt.
125 *
126 * Interrupt might indicate:
127 * - transaction completed, either by triggering IOC, SPD, or an error
128 * - some kind of device error
129 * - resume from suspend state (not implemented)
130 */
131void hc_interrupt(hc_t *instance, uint16_t status)
132{
133 assert(instance);
134 /* Lower 2 bits are transaction error and transaction complete */
135 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) {
136 LIST_INITIALIZE(done);
137 transfer_list_remove_finished(
138 &instance->transfers_interrupt, &done);
139 transfer_list_remove_finished(
140 &instance->transfers_control_slow, &done);
141 transfer_list_remove_finished(
142 &instance->transfers_control_full, &done);
143 transfer_list_remove_finished(
144 &instance->transfers_bulk_full, &done);
145
146 while (!list_empty(&done)) {
147 link_t *item = list_first(&done);
148 list_remove(item);
149 uhci_transfer_batch_t *batch =
150 uhci_transfer_batch_from_link(item);
151 uhci_transfer_batch_finish_dispose(batch);
152 }
153 }
154 /* Resume interrupts are not supported */
155 if (status & UHCI_STATUS_RESUME) {
156 usb_log_error("Resume interrupt!\n");
157 }
158
159 /* Bits 4 and 5 indicate hc error */
160 if (status & (UHCI_STATUS_PROCESS_ERROR | UHCI_STATUS_SYSTEM_ERROR)) {
161 usb_log_error("UHCI hardware failure!.\n");
162 ++instance->hw_failures;
163 transfer_list_abort_all(&instance->transfers_interrupt);
164 transfer_list_abort_all(&instance->transfers_control_slow);
165 transfer_list_abort_all(&instance->transfers_control_full);
166 transfer_list_abort_all(&instance->transfers_bulk_full);
167
168 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
169 /* reinitialize hw, this triggers virtual disconnect*/
170 hc_init_hw(instance);
171 } else {
172 usb_log_fatal("Too many UHCI hardware failures!.\n");
173 hc_fini(instance);
174 }
175 }
176}
177
178/** Initialize UHCI hc driver structure
179 *
180 * @param[in] instance Memory place to initialize.
181 * @param[in] regs Address of I/O control registers.
182 * @param[in] reg_size Size of I/O control registers.
183 * @param[in] interrupts True if hw interrupts should be used.
184 * @return Error code.
185 * @note Should be called only once on any structure.
186 *
187 * Initializes memory structures, starts up hw, and launches debugger and
188 * interrupt fibrils.
189 */
190int hc_init(hc_t *instance, void *regs, size_t reg_size, bool interrupts)
191{
192 assert(reg_size >= sizeof(uhci_regs_t));
193 int ret;
194
195#define CHECK_RET_RETURN(ret, message...) \
196 if (ret != EOK) { \
197 usb_log_error(message); \
198 return ret; \
199 } else (void) 0
200
201 instance->hw_interrupts = interrupts;
202 instance->hw_failures = 0;
203
204 /* allow access to hc control registers */
205 uhci_regs_t *io;
206 ret = pio_enable(regs, reg_size, (void **)&io);
207 CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p: %s.\n",
208 io, str_error(ret));
209 instance->registers = io;
210 usb_log_debug(
211 "Device registers at %p (%zuB) accessible.\n", io, reg_size);
212
213 ret = hc_init_mem_structures(instance);
214 CHECK_RET_RETURN(ret,
215 "Failed to initialize UHCI memory structures: %s.\n",
216 str_error(ret));
217
218#undef CHECK_RET_RETURN
219
220 hcd_init(&instance->generic, USB_SPEED_FULL,
221 BANDWIDTH_AVAILABLE_USB11, bandwidth_count_usb11);
222
223 instance->generic.private_data = instance;
224 instance->generic.schedule = hc_schedule;
225 instance->generic.ep_add_hook = NULL;
226
227 hc_init_hw(instance);
228 if (!interrupts) {
229 instance->interrupt_emulator =
230 fibril_create(hc_interrupt_emulator, instance);
231 fibril_add_ready(instance->interrupt_emulator);
232 }
233 (void)hc_debug_checker;
234
235 return EOK;
236}
237
238/** Initialize UHCI hc hw resources.
239 *
240 * @param[in] instance UHCI structure to use.
241 * For magic values see UHCI Design Guide
242 */
243void hc_init_hw(const hc_t *instance)
244{
245 assert(instance);
246 uhci_regs_t *registers = instance->registers;
247
248 /* Reset everything, who knows what touched it before us */
249 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
250 async_usleep(50000); /* 50ms according to USB spec(root hub reset) */
251 pio_write_16(&registers->usbcmd, 0);
252
253 /* Reset hc, all states and counters. Hope that hw is not broken */
254 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
255 do { async_usleep(10); }
256 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
257
258 /* Set frame to exactly 1ms */
259 pio_write_8(&registers->sofmod, 64);
260
261 /* Set frame list pointer */
262 const uint32_t pa = addr_to_phys(instance->frame_list);
263 pio_write_32(&registers->flbaseadd, pa);
264
265 if (instance->hw_interrupts) {
266 /* Enable all interrupts, but resume interrupt */
267 pio_write_16(&instance->registers->usbintr,
268 UHCI_INTR_ALLOW_INTERRUPTS);
269 }
270
271 const uint16_t cmd = pio_read_16(&registers->usbcmd);
272 if (cmd != 0)
273 usb_log_warning("Previous command value: %x.\n", cmd);
274
275 /* Start the hc with large(64B) packet FSBR */
276 pio_write_16(&registers->usbcmd,
277 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
278}
279
280/** Initialize UHCI hc memory structures.
281 *
282 * @param[in] instance UHCI structure to use.
283 * @return Error code
284 * @note Should be called only once on any structure.
285 *
286 * Structures:
287 * - transfer lists (queue heads need to be accessible by the hw)
288 * - frame list page (needs to be one UHCI hw accessible 4K page)
289 */
290int hc_init_mem_structures(hc_t *instance)
291{
292 assert(instance);
293
294 /* Init USB frame list page */
295 instance->frame_list = get_page();
296 if (!instance->frame_list) {
297 return ENOMEM;
298 }
299 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
300
301 /* Init transfer lists */
302 int ret = hc_init_transfer_lists(instance);
303 if (ret != EOK) {
304 usb_log_error("Failed to initialize transfer lists.\n");
305 return_page(instance->frame_list);
306 return ENOMEM;
307 }
308 usb_log_debug("Initialized transfer lists.\n");
309
310
311 /* Set all frames to point to the first queue head */
312 const uint32_t queue = LINK_POINTER_QH(
313 addr_to_phys(instance->transfers_interrupt.queue_head));
314
315 for (unsigned i = 0; i < UHCI_FRAME_LIST_COUNT; ++i) {
316 instance->frame_list[i] = queue;
317 }
318
319 return EOK;
320}
321
322/** Initialize UHCI hc transfer lists.
323 *
324 * @param[in] instance UHCI structure to use.
325 * @return Error code
326 * @note Should be called only once on any structure.
327 *
328 * Initializes transfer lists and sets them in one chain to support proper
329 * USB scheduling. Sets pointer table for quick access.
330 */
331int hc_init_transfer_lists(hc_t *instance)
332{
333 assert(instance);
334#define SETUP_TRANSFER_LIST(type, name) \
335do { \
336 int ret = transfer_list_init(&instance->transfers_##type, name); \
337 if (ret != EOK) { \
338 usb_log_error("Failed to setup %s transfer list: %s.\n", \
339 name, str_error(ret)); \
340 transfer_list_fini(&instance->transfers_bulk_full); \
341 transfer_list_fini(&instance->transfers_control_full); \
342 transfer_list_fini(&instance->transfers_control_slow); \
343 transfer_list_fini(&instance->transfers_interrupt); \
344 return ret; \
345 } \
346} while (0)
347
348 SETUP_TRANSFER_LIST(bulk_full, "BULK FULL");
349 SETUP_TRANSFER_LIST(control_full, "CONTROL FULL");
350 SETUP_TRANSFER_LIST(control_slow, "CONTROL LOW");
351 SETUP_TRANSFER_LIST(interrupt, "INTERRUPT");
352#undef SETUP_TRANSFER_LIST
353 /* Connect lists into one schedule */
354 transfer_list_set_next(&instance->transfers_control_full,
355 &instance->transfers_bulk_full);
356 transfer_list_set_next(&instance->transfers_control_slow,
357 &instance->transfers_control_full);
358 transfer_list_set_next(&instance->transfers_interrupt,
359 &instance->transfers_control_slow);
360
361 /*FSBR, This feature is not needed (adds no benefit) and is supposedly
362 * buggy on certain hw, enable at your own risk. */
363#ifdef FSBR
364 transfer_list_set_next(&instance->transfers_bulk_full,
365 &instance->transfers_control_full);
366#endif
367
368 /* Assign pointers to be used during scheduling */
369 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
370 &instance->transfers_interrupt;
371 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
372 &instance->transfers_interrupt;
373 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
374 &instance->transfers_control_full;
375 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
376 &instance->transfers_control_slow;
377 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
378 &instance->transfers_bulk_full;
379
380 return EOK;
381#undef CHECK_RET_CLEAR_RETURN
382}
383
384/** Schedule batch for execution.
385 *
386 * @param[in] instance UHCI structure to use.
387 * @param[in] batch Transfer batch to schedule.
388 * @return Error code
389 *
390 * Checks for bandwidth availability and appends the batch to the proper queue.
391 */
392int hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch)
393{
394 assert(hcd);
395 hc_t *instance = hcd->private_data;
396 assert(instance);
397 assert(batch);
398 uhci_transfer_batch_t *uhci_batch = uhci_transfer_batch_get(batch);
399 if (!uhci_batch) {
400 usb_log_error("Failed to create UHCI transfer structures.\n");
401 return ENOMEM;
402 }
403
404 transfer_list_t *list =
405 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
406 assert(list);
407 transfer_list_add_batch(list, uhci_batch);
408
409 return EOK;
410}
411
412/** Polling function, emulates interrupts.
413 *
414 * @param[in] arg UHCI hc structure to use.
415 * @return EOK (should never return)
416 */
417int hc_interrupt_emulator(void* arg)
418{
419 usb_log_debug("Started interrupt emulator.\n");
420 hc_t *instance = arg;
421 assert(instance);
422
423 while (1) {
424 /* Read and clear status register */
425 uint16_t status = pio_read_16(&instance->registers->usbsts);
426 pio_write_16(&instance->registers->usbsts, status);
427 if (status != 0)
428 usb_log_debug2("UHCI status: %x.\n", status);
429 hc_interrupt(instance, status);
430 async_usleep(UHCI_INT_EMULATOR_TIMEOUT);
431 }
432 return EOK;
433}
434
435/** Debug function, checks consistency of memory structures.
436 *
437 * @param[in] arg UHCI structure to use.
438 * @return EOK (should never return)
439 */
440int hc_debug_checker(void *arg)
441{
442 hc_t *instance = arg;
443 assert(instance);
444
445#define QH(queue) \
446 instance->transfers_##queue.queue_head
447
448 while (1) {
449 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
450 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
451 const uint16_t intr =
452 pio_read_16(&instance->registers->usbintr);
453
454 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
455 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
456 cmd, sts, intr);
457 }
458
459 const uintptr_t frame_list =
460 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
461 if (frame_list != addr_to_phys(instance->frame_list)) {
462 usb_log_debug("Framelist address: %p vs. %p.\n",
463 (void *) frame_list,
464 (void *) addr_to_phys(instance->frame_list));
465 }
466
467 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
468
469 uintptr_t expected_pa = instance->frame_list[frnum]
470 & LINK_POINTER_ADDRESS_MASK;
471 uintptr_t real_pa = addr_to_phys(QH(interrupt));
472 if (expected_pa != real_pa) {
473 usb_log_debug("Interrupt QH: %p (frame %d) vs. %p.\n",
474 (void *) expected_pa, frnum, (void *) real_pa);
475 }
476
477 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
478 real_pa = addr_to_phys(QH(control_slow));
479 if (expected_pa != real_pa) {
480 usb_log_debug("Control Slow QH: %p vs. %p.\n",
481 (void *) expected_pa, (void *) real_pa);
482 }
483
484 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
485 real_pa = addr_to_phys(QH(control_full));
486 if (expected_pa != real_pa) {
487 usb_log_debug("Control Full QH: %p vs. %p.\n",
488 (void *) expected_pa, (void *) real_pa);
489 }
490
491 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
492 real_pa = addr_to_phys(QH(bulk_full));
493 if (expected_pa != real_pa ) {
494 usb_log_debug("Bulk QH: %p vs. %p.\n",
495 (void *) expected_pa, (void *) real_pa);
496 }
497 async_usleep(UHCI_DEBUGER_TIMEOUT);
498 }
499 return EOK;
500#undef QH
501}
502/**
503 * @}
504 */
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