Changeset 811770c in mainline for kernel/arch/amd64/include/arch/asm.h

Timestamp:

2016-05-05T12:06:04Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

57c2a87

Parents:

0f17bff

Message:

Avoid magic numbers and specialized functions to set/get register bits

File:

• kernel/arch/amd64/include/arch/asm.h (modified) (6 diffs)

kernel/arch/amd64/include/arch/asm.h

@@ -208 +208 @@
 }
 
-/** Enable interrupts.
- *
- * Enable interrupts and return previous
- * value of EFLAGS.
- *
- * @return Old interrupt priority level.
- *
- */
-NO_TRACE static inline ipl_t interrupts_enable(void) {
-        ipl_t v;
-        
+NO_TRACE static inline uint64_t read_rflags(void)
+{
+        uint64_t rflags;
+
         asm volatile (
                 "pushfq\n"
                 "popq %[v]\n"
-                "sti\n"
-                : [v] "=r" (v)
-        );
-        
-        return v;
+                : [v] "=r" (rflags)
+        );
+
+        return rflags;
+}
+
+NO_TRACE static inline void write_rflags(uint64_t rflags)
+{
+        asm volatile (
+                "pushq %[v]\n"
+                "popfq\n"
+                :: [v] "r" (rflags)
+        );
+}
+
+/** Return interrupt priority level.
+ *
+ * Return the current interrupt priority level.
+ *
+ * @return Current interrupt priority level.
+ */
+NO_TRACE static inline ipl_t interrupts_read(void) {
+        return (ipl_t) read_rflags();
+}
+
+/** Enable interrupts.
+ *
+ * Enable interrupts and return the previous interrupt priority level.
+ *
+ * @return Old interrupt priority level.
+ */
+NO_TRACE static inline ipl_t interrupts_enable(void) {
+        ipl_t ipl = interrupts_read();
+        
+        asm volatile ("sti\n");
+        
+        return ipl;
 }
 
 /** Disable interrupts.
  *
- * Disable interrupts and return previous
- * value of EFLAGS.
+ * Disable interrupts and return the previous interrupt priority level.
  *
  * @return Old interrupt priority level.
- *
  */
 NO_TRACE static inline ipl_t interrupts_disable(void) {
-        ipl_t v;
-        
-        asm volatile (
-                "pushfq\n"
-                "popq %[v]\n"
-                "cli\n"
-                : [v] "=r" (v)
-        );
-        
-        return v;
+        ipl_t ipl = interrupts_read();
+        
+        asm volatile ("cli\n");
+        
+        return ipl;
 }
 
 /** Restore interrupt priority level.
  *
- * Restore EFLAGS.
+ * Restore the previously save interrupt priority level.
  *
  * @param ipl Saved interrupt priority level.
@@ -258 +276 @@
  */
 NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
-        asm volatile (
-                "pushq %[ipl]\n"
-                "popfq\n"
-                :: [ipl] "r" (ipl)
-        );
-}
-
-/** Return interrupt priority level.
- *
- * Return EFLAFS.
- *
- * @return Current interrupt priority level.
- *
- */
-NO_TRACE static inline ipl_t interrupts_read(void) {
-        ipl_t v;
-        
-        asm volatile (
-                "pushfq\n"
-                "popq %[v]\n"
-                : [v] "=r" (v)
-        );
-        
-        return v;
+        write_rflags((uint64_t) ipl);
 }
 
@@ -291 +286 @@
 NO_TRACE static inline bool interrupts_disabled(void)
 {
-        ipl_t v;
-        
-        asm volatile (
-                "pushfq\n"
-                "popq %[v]\n"
-                : [v] "=r" (v)
-        );
-        
-        return ((v & RFLAGS_IF) == 0);
+        return ((read_rflags() & RFLAGS_IF) == 0);
 }
 
@@ -324 +311 @@
         
         return ((uint64_t) dx << 32) | ax;
-}
-
-/** Enable local APIC
- *
- * Enable local APIC in MSR.
- *
- */
-NO_TRACE static inline void enable_l_apic_in_msr(void)
-{
-        asm volatile (
-                "movl $0x1b, %%ecx\n"
-                "rdmsr\n"
-                "orl $(1 << 11),%%eax\n"
-                "orl $(0xfee00000),%%eax\n"
-                "wrmsr\n"
-                ::: "%eax", "%ecx", "%edx"
-        );
 }
 
@@ -426 +396 @@
 
 GEN_READ_REG(cr0)
+GEN_WRITE_REG(cr0)
 GEN_READ_REG(cr2)
 GEN_READ_REG(cr3)
 GEN_WRITE_REG(cr3)
+GEN_READ_REG(cr4)
+GEN_WRITE_REG(cr4)
 
 GEN_READ_REG(dr0)
@@ -512 +485 @@
 extern uintptr_t int_63;
 
+extern void enable_l_apic_in_msr(void);
+
 #endif