- Timestamp:
- 2005-12-15T16:10:19Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- b4cad8b2
- Parents:
- 7dd2561
- Location:
- arch
- Files:
-
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/include/asm.h
r7dd2561 r80d2bdb 55 55 56 56 57 static inline __u8 inb(__u16 port) 58 { 59 __u8 out; 60 61 __asm__ volatile ( 62 "mov %1, %%dx\n" 63 "inb %%dx,%%al\n" 64 "mov %%al, %0\n" 65 :"=m"(out) 66 :"m"(port) 67 :"%rdx","%rax" 68 ); 69 return out; 70 } 71 72 static inline __u8 outb(__u16 port,__u8 b) 73 { 74 __asm__ volatile ( 75 "mov %0,%%dx\n" 76 "mov %1,%%al\n" 77 "outb %%al,%%dx\n" 78 : 79 :"m"( port), "m" (b) 80 :"%rdx","%rax" 81 ); 82 } 57 /** Byte from port 58 * 59 * Get byte from port 60 * 61 * @param port Port to read from 62 * @return Value read 63 */ 64 static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } 65 66 /** Byte to port 67 * 68 * Output byte to port 69 * 70 * @param port Port to write to 71 * @param val Value to write 72 */ 73 static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } 83 74 84 75 /** Enable interrupts. -
arch/amd64/src/cpu/cpu.c
r7dd2561 r80d2bdb 126 126 { 127 127 cpu_info_t info; 128 int i;129 128 130 129 CPU->arch.vendor = VendorUnknown; -
arch/ia32/include/atomic.h
r7dd2561 r80d2bdb 32 32 #include <arch/types.h> 33 33 34 typedef volatile __u32 atomic_t; 34 typedef struct { volatile __u32 count; } atomic_t; 35 36 static inline void atomic_set(atomic_t *val, __u32 i) 37 { 38 val->count = i; 39 } 40 41 static inline __u32 atomic_get(atomic_t *val) 42 { 43 return val->count; 44 } 35 45 36 46 static inline void atomic_inc(atomic_t *val) { 37 47 #ifdef CONFIG_SMP 38 __asm__ volatile ("lock incl %0\n" : "=m" ( *val));48 __asm__ volatile ("lock incl %0\n" : "=m" (val->count)); 39 49 #else 40 __asm__ volatile ("incl %0\n" : "=m" ( *val));50 __asm__ volatile ("incl %0\n" : "=m" (val->count)); 41 51 #endif /* CONFIG_SMP */ 42 52 } … … 44 54 static inline void atomic_dec(atomic_t *val) { 45 55 #ifdef CONFIG_SMP 46 __asm__ volatile ("lock decl %0\n" : "=m" ( *val));56 __asm__ volatile ("lock decl %0\n" : "=m" (val->count)); 47 57 #else 48 __asm__ volatile ("decl %0\n" : "=m" ( *val));58 __asm__ volatile ("decl %0\n" : "=m" (val->count)); 49 59 #endif /* CONFIG_SMP */ 50 60 } … … 56 66 "movl $1, %0\n" 57 67 "lock xaddl %0, %1\n" 58 : "=r"(r), "=m" ( *val)68 : "=r"(r), "=m" (val->count) 59 69 ); 60 70 return r; … … 77 87 #define atomic_dec_post(val) (atomic_dec_pre(val)-1) 78 88 79 static inline int test_and_set( volatile int *val) {89 static inline int test_and_set(atomic_t *val) { 80 90 int v; 81 91 … … 83 93 "movl $1, %0\n" 84 94 "xchgl %0, %1\n" 85 : "=r" (v),"=m" ( *val)95 : "=r" (v),"=m" (val->count) 86 96 ); 87 97 -
arch/ia32/src/fmath.c
r7dd2561 r80d2bdb 63 63 fmath_ld_union_t fmath_ld_union_int; 64 64 signed short exp; 65 __u64 mask,mantisa; 65 __u64 mask; 66 // __u64 mantisa; 66 67 int i; 67 68 -
arch/ia32/src/mm/frame.c
r7dd2561 r80d2bdb 44 44 void frame_arch_init(void) 45 45 { 46 zone_t *z;47 46 __u8 i; 48 47 -
arch/ia32/src/smp/smp.c
r7dd2561 r80d2bdb 88 88 void kmp(void *arg) 89 89 { 90 __address src, dst;91 90 int i; 92 91 -
arch/ia64/include/atomic.h
r7dd2561 r80d2bdb 32 32 #include <arch/types.h> 33 33 34 typedef volatile __u64atomic_t;34 typedef struct { volatile __u64 count; } atomic_t; 35 35 36 36 static inline atomic_t atomic_add(atomic_t *val, int imm) … … 39 39 40 40 41 __asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" ( *val) : "i" (imm));41 __asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm)); 42 42 43 43 return v; 44 } 45 46 static inline void atomic_set(atomic_t *val, __u64 i) 47 { 48 val->count = i; 49 } 50 51 static inline __u32 atomic_get(atomic_t *val) 52 { 53 return val->count; 44 54 } 45 55 -
arch/mips32/include/atomic.h
r7dd2561 r80d2bdb 42 42 43 43 44 typedef volatile __u32atomic_t;44 typedef struct { volatile __u32 count; } atomic_t; 45 45 46 46 /* Atomic addition of immediate value. … … 63 63 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ 64 64 /* nop */ /* nop is inserted automatically by compiler */ 65 : "=r" (tmp), "=m" ( *val), "=r" (v)65 : "=r" (tmp), "=m" (val->count), "=r" (v) 66 66 : "i" (i), "i" (0) 67 67 ); … … 70 70 } 71 71 72 /* Reads/writes are atomic on mips for 4-bytes */ 73 74 static inline void atomic_set(atomic_t *val, __u32 i) 75 { 76 val->count = i; 77 } 78 79 static inline __u32 atomic_get(atomic_t *val) 80 { 81 return val->count; 82 } 72 83 73 84 #endif -
arch/mips32/src/drivers/arc.c
r7dd2561 r80d2bdb 189 189 arc_putchar('C'); 190 190 arc_putchar('\n'); 191 192 return 0; 191 193 } 192 194 … … 287 289 __address base; 288 290 size_t basesize; 289 unsigned int i,j;290 291 291 292 desc = arc_entry->getmemorydescriptor(NULL); -
arch/mips32/src/drivers/serial.c
r7dd2561 r80d2bdb 39 39 static void serial_write(chardev_t *d, const char ch) 40 40 { 41 int i;42 41 serial_t *sd = (serial_t *)d->data; 43 42 -
arch/ppc32/include/atomic.h
r7dd2561 r80d2bdb 32 32 #include <arch/types.h> 33 33 34 typedef volatile __u32atomic_t;34 typedef struct { volatile __u32 count; } atomic_t; 35 35 36 36 /* … … 40 40 41 41 static inline void atomic_inc(atomic_t *val) { 42 *val++;42 val->count++; 43 43 } 44 44 45 45 static inline void atomic_dec(atomic_t *val) { 46 *val--; 46 val->count--; 47 } 48 49 static inline void atomic_set(atomic_t *val, __u32 i) 50 { 51 val->count = i; 52 } 53 54 static inline __u32 atomic_get(atomic_t *val) 55 { 56 return val->count; 47 57 } 48 58 -
arch/sparc64/include/atomic.h
r7dd2561 r80d2bdb 32 32 #include <arch/types.h> 33 33 34 typedef volatile __u64atomic_t;34 typedef struct { volatile __u64 count; } atomic_t; 35 35 36 36 /* … … 40 40 41 41 static inline void atomic_inc(atomic_t *val) { 42 *val++;42 val->count++; 43 43 } 44 44 45 45 static inline void atomic_dec(atomic_t *val) { 46 *val--;46 val->count--; 47 47 } 48 48
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